Hoai V. Ho

Array ( [id] => 980447 [patent_doc_number] => 06930941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Semiconductor memory device having potential amplitude of global bit line pair restricted to partial swing' [patent_app_type] => utility [patent_app_number] => 10/677012 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 10814 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930941.pdf [firstpage_image] =>[orig_patent_app_number] => 10677012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 547319 [patent_doc_number] => 07177183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Multiple twin cell non-volatile memory array and logic block structure and method therefor' [patent_app_type] => utility [patent_app_number] => 10/675212 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7942 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/177/07177183.pdf [firstpage_image] =>[orig_patent_app_number] => 10675212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7268788 [patent_doc_number] => 20040057306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Non-volatile memory device with erase address register' [patent_app_type] => new [patent_app_number] => 10/672312 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4645 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20040057306.pdf [firstpage_image] =>[orig_patent_app_number] => 10672312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 713970 [patent_doc_number] => 07057933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Non-volatile memory device with erase address register' [patent_app_type] => utility [patent_app_number] => 10/672122 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4622 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057933.pdf [firstpage_image] =>[orig_patent_app_number] => 10672122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1054718 [patent_doc_number] => 06859377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Dynamic associative memory device' [patent_app_type] => utility [patent_app_number] => 10/668310 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5772 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859377.pdf [firstpage_image] =>[orig_patent_app_number] => 10668310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1051630 [patent_doc_number] => 06862202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Low power memory module using restricted device activation' [patent_app_type] => utility [patent_app_number] => 10/669663 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2983 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862202.pdf [firstpage_image] =>[orig_patent_app_number] => 10669663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1057935 [patent_doc_number] => 06856549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Non-volatile semiconductor memory device attaining high data transfer rate' [patent_app_type] => utility [patent_app_number] => 10/665010 [patent_app_country] => US [patent_app_date] => 2003-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10923 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856549.pdf [firstpage_image] =>[orig_patent_app_number] => 10665010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1023651 [patent_doc_number] => 06888757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Method for erasing a memory cell' [patent_app_type] => utility [patent_app_number] => 10/656251 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3107 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888757.pdf [firstpage_image] =>[orig_patent_app_number] => 10656251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7146373 [patent_doc_number] => 20040170060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Semiconductor storage device preventing data change due to accumulative disturbance' [patent_app_type] => new [patent_app_number] => 10/644910 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5512 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20040170060.pdf [firstpage_image] =>[orig_patent_app_number] => 10644910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 936202 [patent_doc_number] => 06975552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Hybrid open and folded digit line architecture' [patent_app_type] => utility [patent_app_number] => 10/644610 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5008 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975552.pdf [firstpage_image] =>[orig_patent_app_number] => 10644610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7146396 [patent_doc_number] => 20040170067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Semiconductor memory device permitting control of internal power supply voltage in packaged state' [patent_app_type] => new [patent_app_number] => 10/642213 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3162 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20040170067.pdf [firstpage_image] =>[orig_patent_app_number] => 10642213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6970670 [patent_doc_number] => 20050036380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Method and system of adjusting DRAM refresh interval' [patent_app_type] => utility [patent_app_number] => 10/640313 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 882 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20050036380.pdf [firstpage_image] =>[orig_patent_app_number] => 10640313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 959450 [patent_doc_number] => 06954398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Semiconductor memory device including subword drivers' [patent_app_type] => utility [patent_app_number] => 10/633710 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5163 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954398.pdf [firstpage_image] =>[orig_patent_app_number] => 10633710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 977313 [patent_doc_number] => 06934194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Nonvolatile memory having a trap layer' [patent_app_type] => utility [patent_app_number] => 10/631812 [patent_app_country] => US [patent_app_date] => 2003-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 8548 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934194.pdf [firstpage_image] =>[orig_patent_app_number] => 10631812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7374937 [patent_doc_number] => 20040027910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Method of generating initializing signal in semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/632572 [patent_app_country] => US [patent_app_date] => 2003-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4871 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027910.pdf [firstpage_image] =>[orig_patent_app_number] => 10632572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 997813 [patent_doc_number] => 06914814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Dedicated redundancy circuits for different operations in a flash memory device and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 10/630116 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5033 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914814.pdf [firstpage_image] =>[orig_patent_app_number] => 10630116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7162906 [patent_doc_number] => 20040076039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information' [patent_app_type] => new [patent_app_number] => 10/631412 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2754 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20040076039.pdf [firstpage_image] =>[orig_patent_app_number] => 10631412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7244243 [patent_doc_number] => 20040257897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Semiconductor storage device' [patent_app_type] => new [patent_app_number] => 10/624814 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5565 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257897.pdf [firstpage_image] =>[orig_patent_app_number] => 10624814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1000721 [patent_doc_number] => 06912149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Ferroelectric memory device and method for reading data from the same' [patent_app_type] => utility [patent_app_number] => 10/620614 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 22908 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912149.pdf [firstpage_image] =>[orig_patent_app_number] => 10620614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7352390 [patent_doc_number] => 20040013000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Nonvolatile semiconductor memory and method of operating the same' [patent_app_type] => new [patent_app_number] => 10/618712 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14255 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20040013000.pdf [firstpage_image] =>[orig_patent_app_number] => 10618712 [rel_patent_id] =>[rel_patent_doc_number] =>)