Hoai V. Ho

Array ( [id] => 6644054 [patent_doc_number] => 20030007391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Evaluation circuit for a DRAM' [patent_app_type] => new [patent_app_number] => 10/190814 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5005 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007391.pdf [firstpage_image] =>[orig_patent_app_number] => 10190814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7425684 [patent_doc_number] => 20040001359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Hold-up power supply for flash memory' [patent_app_type] => new [patent_app_number] => 10/186516 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20040001359.pdf [firstpage_image] =>[orig_patent_app_number] => 10186516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1131022 [patent_doc_number] => 06791892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Method of generating an initializing signal during power-up of semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/187718 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3458 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791892.pdf [firstpage_image] =>[orig_patent_app_number] => 10187718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6644048 [patent_doc_number] => 20030007390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Data output circuit of a memory device' [patent_app_type] => new [patent_app_number] => 10/183817 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1472 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007390.pdf [firstpage_image] =>[orig_patent_app_number] => 10183817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 763738 [patent_doc_number] => 07012843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Device for driving a memory cell of a memory module by means of a charge store' [patent_app_type] => utility [patent_app_number] => 10/180818 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4406 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012843.pdf [firstpage_image] =>[orig_patent_app_number] => 10180818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6714776 [patent_doc_number] => 20030026124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/178411 [patent_app_country] => US [patent_app_date] => 2002-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5995 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20030026124.pdf [firstpage_image] =>[orig_patent_app_number] => 10178411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1268865 [patent_doc_number] => 06661692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B2 [patent_app_number] => 10/179710 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5787 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661692.pdf [firstpage_image] =>[orig_patent_app_number] => 10179710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6687328 [patent_doc_number] => 20030031051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Non-volatile memory' [patent_app_type] => new [patent_app_number] => 10/064216 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6586 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20030031051.pdf [firstpage_image] =>[orig_patent_app_number] => 10064216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6824459 [patent_doc_number] => 20030235081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Nanocrystal write once read only memory for archival storage' [patent_app_type] => new [patent_app_number] => 10/177214 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8807 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235081.pdf [firstpage_image] =>[orig_patent_app_number] => 10177214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1216114 [patent_doc_number] => 06711064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Single-poly EEPROM' [patent_app_type] => B2 [patent_app_number] => 10/064214 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3849 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711064.pdf [firstpage_image] =>[orig_patent_app_number] => 10064214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6824484 [patent_doc_number] => 20030235106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Delay locked loop control circuit' [patent_app_type] => new [patent_app_number] => 10/177218 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4085 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235106.pdf [firstpage_image] =>[orig_patent_app_number] => 10177218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6173062 [patent_doc_number] => 20020154562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/173433 [patent_app_country] => US [patent_app_date] => 2002-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10414 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20020154562.pdf [firstpage_image] =>[orig_patent_app_number] => 10173433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1234549 [patent_doc_number] => 06693844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Sending signal through integrated circuit during setup time' [patent_app_type] => B2 [patent_app_number] => 10/174747 [patent_app_country] => US [patent_app_date] => 2002-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4807 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693844.pdf [firstpage_image] =>[orig_patent_app_number] => 10174747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6455113 [patent_doc_number] => 20020149971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other' [patent_app_type] => new [patent_app_number] => 10/171686 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5318 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149971.pdf [firstpage_image] =>[orig_patent_app_number] => 10171686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1149385 [patent_doc_number] => 06778435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Memory architecture for TCCT-based memory cells' [patent_app_type] => B1 [patent_app_number] => 10/170816 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9384 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/778/06778435.pdf [firstpage_image] =>[orig_patent_app_number] => 10170816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1126944 [patent_doc_number] => 06795332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Semiconductor memory device with memory cells operated by boosted voltage' [patent_app_type] => B2 [patent_app_number] => 10/163310 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 45 [patent_no_of_words] => 9558 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795332.pdf [firstpage_image] =>[orig_patent_app_number] => 10163310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1238790 [patent_doc_number] => 06690603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Microcomputer including a flash memory that is two-way programmable' [patent_app_type] => B2 [patent_app_number] => 10/158901 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 80 [patent_no_of_words] => 31939 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/690/06690603.pdf [firstpage_image] =>[orig_patent_app_number] => 10158901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 973956 [patent_doc_number] => 06937521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Programming and erasing methods for a non-volatile memory cell' [patent_app_type] => utility [patent_app_number] => 10/155216 [patent_app_country] => US [patent_app_date] => 2002-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 32 [patent_no_of_words] => 10995 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/937/06937521.pdf [firstpage_image] =>[orig_patent_app_number] => 10155216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1158290 [patent_doc_number] => 06771537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Nonvolatile semiconductor memory device which stores multi-value information' [patent_app_type] => B2 [patent_app_number] => 10/154853 [patent_app_country] => US [patent_app_date] => 2002-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 17558 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/771/06771537.pdf [firstpage_image] =>[orig_patent_app_number] => 10154853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6812642 [patent_doc_number] => 20030072192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Programming of nonvolatile memory cells' [patent_app_type] => new [patent_app_number] => 10/155217 [patent_app_country] => US [patent_app_date] => 2002-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7675 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20030072192.pdf [firstpage_image] =>[orig_patent_app_number] => 10155217 [rel_patent_id] =>[rel_patent_doc_number] =>)