Hoai V. Ho

Array ( [id] => 6691721 [patent_doc_number] => 20030039153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'EEPROM array and method for operation thereof' [patent_app_type] => new [patent_app_number] => 10/155215 [patent_app_country] => US [patent_app_date] => 2002-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5518 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20030039153.pdf [firstpage_image] =>[orig_patent_app_number] => 10155215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6257170 [patent_doc_number] => 20020186586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Reading circuit for a non-volatile memory' [patent_app_type] => new [patent_app_number] => 10/154417 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3500 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20020186586.pdf [firstpage_image] =>[orig_patent_app_number] => 10154417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6257170 [patent_doc_number] => 20020186586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Reading circuit for a non-volatile memory' [patent_app_type] => new [patent_app_number] => 10/154417 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3500 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20020186586.pdf [firstpage_image] =>[orig_patent_app_number] => 10154417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1185353 [patent_doc_number] => 06738297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Low voltage current reference' [patent_app_type] => B2 [patent_app_number] => 10/146112 [patent_app_country] => US [patent_app_date] => 2002-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3107 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738297.pdf [firstpage_image] =>[orig_patent_app_number] => 10146112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5842229 [patent_doc_number] => 20020131288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Associative memory for accomplishing longest coincidence data detection by two comparing operations' [patent_app_type] => new [patent_app_number] => 10/142891 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7041 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20020131288.pdf [firstpage_image] =>[orig_patent_app_number] => 10142891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6422999 [patent_doc_number] => 20020126538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Data read/write method' [patent_app_type] => new [patent_app_number] => 10/142823 [patent_app_country] => US [patent_app_date] => 2002-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3662 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126538.pdf [firstpage_image] =>[orig_patent_app_number] => 10142823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6687358 [patent_doc_number] => 20030031081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Semiconductor memory device operating in synchronization with data strobe signal' [patent_app_type] => new [patent_app_number] => 10/135512 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5271 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20030031081.pdf [firstpage_image] =>[orig_patent_app_number] => 10135512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1172644 [patent_doc_number] => 06760246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method of writing ferroelectric field effect transistor' [patent_app_type] => B1 [patent_app_number] => 10/136210 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 43 [patent_no_of_words] => 6365 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760246.pdf [firstpage_image] =>[orig_patent_app_number] => 10136210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1145346 [patent_doc_number] => 06781896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'MRAM semiconductor memory configuration with redundant cell arrays' [patent_app_type] => B2 [patent_app_number] => 10/135416 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2706 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781896.pdf [firstpage_image] =>[orig_patent_app_number] => 10135416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6371827 [patent_doc_number] => 20020118584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/134546 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8672 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20020118584.pdf [firstpage_image] =>[orig_patent_app_number] => 10134546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1398590 [patent_doc_number] => 06556502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Memory circuitry for programmable logic integrated circuit devices' [patent_app_type] => B2 [patent_app_number] => 10/134886 [patent_app_country] => US [patent_app_date] => 2002-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6158 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556502.pdf [firstpage_image] =>[orig_patent_app_number] => 10134886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180206 [patent_doc_number] => 06751127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Systems and methods for refreshing non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 10/132118 [patent_app_country] => US [patent_app_date] => 2002-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3161 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751127.pdf [firstpage_image] =>[orig_patent_app_number] => 10132118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6395592 [patent_doc_number] => 20020181270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Configuration for evaluating a signal which is read from a ferroelectric storage capacitor' [patent_app_type] => new [patent_app_number] => 10/127616 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2160 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20020181270.pdf [firstpage_image] =>[orig_patent_app_number] => 10127616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6808149 [patent_doc_number] => 20030198088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Voltage detection circuit and method for semiconductor memory devices' [patent_app_type] => new [patent_app_number] => 10/125210 [patent_app_country] => US [patent_app_date] => 2002-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4314 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20030198088.pdf [firstpage_image] =>[orig_patent_app_number] => 10125210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6519879 [patent_doc_number] => 20020136052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Programmable memory device' [patent_app_type] => new [patent_app_number] => 10/121110 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2397 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20020136052.pdf [firstpage_image] =>[orig_patent_app_number] => 10121110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1199317 [patent_doc_number] => 06728139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Programmable semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 10/118335 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 7053 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728139.pdf [firstpage_image] =>[orig_patent_app_number] => 10118335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6527159 [patent_doc_number] => 20020109539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Multi-level non-volatile semiconductor memory device with verify voltages having a smart temperature coefficient' [patent_app_type] => new [patent_app_number] => 10/117120 [patent_app_country] => US [patent_app_date] => 2002-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11742 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20020109539.pdf [firstpage_image] =>[orig_patent_app_number] => 10117120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6422874 [patent_doc_number] => 20020126525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Circuit configuration for evaluating the information content of a memory cell' [patent_app_type] => new [patent_app_number] => 10/113417 [patent_app_country] => US [patent_app_date] => 2002-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6874 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126525.pdf [firstpage_image] =>[orig_patent_app_number] => 10113417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 547483 [patent_doc_number] => 07177196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells' [patent_app_type] => utility [patent_app_number] => 10/073999 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 81 [patent_no_of_words] => 61488 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/177/07177196.pdf [firstpage_image] =>[orig_patent_app_number] => 10073999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6272681 [patent_doc_number] => 20020105834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Doublel-bit non-voltatile memory unit and corresponding data read/write method' [patent_app_type] => new [patent_app_number] => 10/074989 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3662 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105834.pdf [firstpage_image] =>[orig_patent_app_number] => 10074989 [rel_patent_id] =>[rel_patent_doc_number] =>)