
Hoai V. Ho
Examiner (ID: 15701)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2312, 2511 |
| Total Applications | 2584 |
| Issued Applications | 2371 |
| Pending Applications | 99 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6859929
[patent_doc_number] => 20030090937
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-15
[patent_title] => 'DRAM-based flash memory unit'
[patent_app_type] => new
[patent_app_number] => 09/987214
[patent_app_country] => US
[patent_app_date] => 2001-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1705
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20030090937.pdf
[firstpage_image] =>[orig_patent_app_number] => 09987214
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/987214 | DRAM-based flash memory unit | Nov 13, 2001 | Abandoned |
Array
(
[id] => 5998462
[patent_doc_number] => 20020027818
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-07
[patent_title] => 'Semiconductor memory device permitting improved integration density and reduced accessing time'
[patent_app_type] => new
[patent_app_number] => 09/986584
[patent_app_country] => US
[patent_app_date] => 2001-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 13865
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 286
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20020027818.pdf
[firstpage_image] =>[orig_patent_app_number] => 09986584
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/986584 | Semiconductor memory device permitting improved integration density and reduced accessing time | Nov 8, 2001 | Issued |
Array
(
[id] => 1231616
[patent_doc_number] => 06697281
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-24
[patent_title] => 'Byte-selectable EEPROM array utilizing single split-gate transistor for non-volatile storage cell'
[patent_app_type] => B2
[patent_app_number] => 10/010617
[patent_app_country] => US
[patent_app_date] => 2001-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3734
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/697/06697281.pdf
[firstpage_image] =>[orig_patent_app_number] => 10010617
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/010617 | Byte-selectable EEPROM array utilizing single split-gate transistor for non-volatile storage cell | Nov 7, 2001 | Issued |
Array
(
[id] => 1194904
[patent_doc_number] => 06731544
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-04
[patent_title] => 'Method and apparatus for multiple byte or page mode programming of a flash memory array'
[patent_app_type] => B2
[patent_app_number] => 10/039518
[patent_app_country] => US
[patent_app_date] => 2001-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 7428
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/731/06731544.pdf
[firstpage_image] =>[orig_patent_app_number] => 10039518
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/039518 | Method and apparatus for multiple byte or page mode programming of a flash memory array | Nov 7, 2001 | Issued |
Array
(
[id] => 6046043
[patent_doc_number] => 20020167843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-14
[patent_title] => 'Method and apparatus for multiple byte or page mode programming and reading of a flash memory array'
[patent_app_type] => new
[patent_app_number] => 10/035414
[patent_app_country] => US
[patent_app_date] => 2001-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7629
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0167/20020167843.pdf
[firstpage_image] =>[orig_patent_app_number] => 10035414
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/035414 | Method and apparatus for multiple byte or page mode programming of a flash memory array | Nov 7, 2001 | Issued |
Array
(
[id] => 6859932
[patent_doc_number] => 20030090940
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-15
[patent_title] => 'DUAL MODE HIGH VOLTAGE POWER SUPPLY FOR PROVIDING INCREASED SPEED IN PROGRAMMING DURING TESTING OF LOW VOLTAGE NON-VOLATILE MEMORIES'
[patent_app_type] => new
[patent_app_number] => 10/005317
[patent_app_country] => US
[patent_app_date] => 2001-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4168
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20030090940.pdf
[firstpage_image] =>[orig_patent_app_number] => 10005317
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/005317 | Dual mode high voltage power supply for providing increased speed in programming during testing of low voltage non-volatile memories | Nov 5, 2001 | Issued |
Array
(
[id] => 5998451
[patent_doc_number] => 20020027807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-07
[patent_title] => 'Non-volatile memory device'
[patent_app_type] => new
[patent_app_number] => 09/985116
[patent_app_country] => US
[patent_app_date] => 2001-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 58
[patent_figures_cnt] => 58
[patent_no_of_words] => 19812
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20020027807.pdf
[firstpage_image] =>[orig_patent_app_number] => 09985116
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/985116 | Non-volatile memory device | Oct 31, 2001 | Issued |
Array
(
[id] => 6868759
[patent_doc_number] => 20030081448
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-01
[patent_title] => 'High voltage bit/column latch for Vcc operation'
[patent_app_type] => new
[patent_app_number] => 10/039916
[patent_app_country] => US
[patent_app_date] => 2001-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3354
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20030081448.pdf
[firstpage_image] =>[orig_patent_app_number] => 10039916
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/039916 | High voltage bit/column latch for Vcc operation | Oct 28, 2001 | Issued |
Array
(
[id] => 6651953
[patent_doc_number] => 20030076729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-24
[patent_title] => 'Method and apparatus for reducing average power and increasing cache performance by modulating power supplies'
[patent_app_type] => new
[patent_app_number] => 10/045310
[patent_app_country] => US
[patent_app_date] => 2001-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1302
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20030076729.pdf
[firstpage_image] =>[orig_patent_app_number] => 10045310
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/045310 | Method and apparatus for reducing average power and increasing cache performance by modulating power supplies | Oct 23, 2001 | Abandoned |
Array
(
[id] => 1288224
[patent_doc_number] => 06643181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-04
[patent_title] => 'Method for erasing a memory cell'
[patent_app_type] => B2
[patent_app_number] => 09/983510
[patent_app_country] => US
[patent_app_date] => 2001-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5028
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/643/06643181.pdf
[firstpage_image] =>[orig_patent_app_number] => 09983510
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/983510 | Method for erasing a memory cell | Oct 23, 2001 | Issued |
Array
(
[id] => 6816849
[patent_doc_number] => 20030067807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-10
[patent_title] => 'Erasing method for p-channel NROM'
[patent_app_type] => new
[patent_app_number] => 10/035514
[patent_app_country] => US
[patent_app_date] => 2001-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1542
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0067/20030067807.pdf
[firstpage_image] =>[orig_patent_app_number] => 10035514
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/035514 | Erasing method for p-channel NROM | Oct 21, 2001 | Issued |
Array
(
[id] => 6155670
[patent_doc_number] => 20020145907
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-10
[patent_title] => 'Non-volatile semiconductor memory device having word line defect check circuit'
[patent_app_type] => new
[patent_app_number] => 09/982316
[patent_app_country] => US
[patent_app_date] => 2001-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6297
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20020145907.pdf
[firstpage_image] =>[orig_patent_app_number] => 09982316
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/982316 | Non-volatile semiconductor memory device having word line defect check circuit | Oct 17, 2001 | Issued |
Array
(
[id] => 1425774
[patent_doc_number] => 06525970
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-25
[patent_title] => 'Erase method for flash memory'
[patent_app_type] => B2
[patent_app_number] => 09/976232
[patent_app_country] => US
[patent_app_date] => 2001-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 33
[patent_no_of_words] => 7101
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/525/06525970.pdf
[firstpage_image] =>[orig_patent_app_number] => 09976232
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/976232 | Erase method for flash memory | Oct 11, 2001 | Issued |
Array
(
[id] => 1322673
[patent_doc_number] => 06608773
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-19
[patent_title] => 'Programmable resistance memory array'
[patent_app_type] => B2
[patent_app_number] => 09/974590
[patent_app_country] => US
[patent_app_date] => 2001-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 13669
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/608/06608773.pdf
[firstpage_image] =>[orig_patent_app_number] => 09974590
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/974590 | Programmable resistance memory array | Oct 9, 2001 | Issued |
Array
(
[id] => 1425695
[patent_doc_number] => 06525963
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-25
[patent_title] => 'Programmable read-only memory and method for operating the read-only memory'
[patent_app_type] => B2
[patent_app_number] => 09/974618
[patent_app_country] => US
[patent_app_date] => 2001-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4361
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/525/06525963.pdf
[firstpage_image] =>[orig_patent_app_number] => 09974618
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/974618 | Programmable read-only memory and method for operating the read-only memory | Oct 8, 2001 | Issued |
Array
(
[id] => 5887244
[patent_doc_number] => 20020012264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-31
[patent_title] => 'Ferroelectric non-volatile memory device'
[patent_app_type] => new
[patent_app_number] => 09/971988
[patent_app_country] => US
[patent_app_date] => 2001-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 11077
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20020012264.pdf
[firstpage_image] =>[orig_patent_app_number] => 09971988
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/971988 | Ferroelectric non-volatile memory device including a layered structure formed on a substrate | Oct 3, 2001 | Issued |
Array
(
[id] => 5784762
[patent_doc_number] => 20020159287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'Shadow ram cell using a ferroelectric capacitor'
[patent_app_type] => new
[patent_app_number] => 09/964418
[patent_app_country] => US
[patent_app_date] => 2001-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7485
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0159/20020159287.pdf
[firstpage_image] =>[orig_patent_app_number] => 09964418
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/964418 | Shadow ram cell using a ferroelectric capacitor | Sep 27, 2001 | Issued |
Array
(
[id] => 1306144
[patent_doc_number] => 06625052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-23
[patent_title] => 'Write-once polymer memory with e-beam writing and reading'
[patent_app_type] => B2
[patent_app_number] => 09/966014
[patent_app_country] => US
[patent_app_date] => 2001-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3061
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/625/06625052.pdf
[firstpage_image] =>[orig_patent_app_number] => 09966014
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/966014 | Write-once polymer memory with e-beam writing and reading | Sep 26, 2001 | Issued |
Array
(
[id] => 5998460
[patent_doc_number] => 20020027816
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-07
[patent_title] => 'Integrated memory having memory cells and reference cells, and operating method for such a memory'
[patent_app_type] => new
[patent_app_number] => 09/962411
[patent_app_country] => US
[patent_app_date] => 2001-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5090
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20020027816.pdf
[firstpage_image] =>[orig_patent_app_number] => 09962411
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/962411 | Integrated memory having memory cells and reference cells, and operating method for such a memory | Sep 23, 2001 | Issued |
Array
(
[id] => 6590515
[patent_doc_number] => 20020015327
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-07
[patent_title] => 'Low voltage flash EEPROM memory cell with improved data retention'
[patent_app_type] => new
[patent_app_number] => 09/957124
[patent_app_country] => US
[patent_app_date] => 2001-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3578
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 28
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20020015327.pdf
[firstpage_image] =>[orig_patent_app_number] => 09957124
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/957124 | Low voltage flash EEPROM memory cell with improved data retention | Sep 19, 2001 | Issued |