Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19546640 [patent_doc_number] => 20240363676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT [patent_app_type] => utility [patent_app_number] => 18/767205 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767205
SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT Jul 8, 2024 Pending
Array ( [id] => 19546452 [patent_doc_number] => 20240363488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR PACKAGES HAVING THERMAL CONDUCTIVE PATTERN [patent_app_type] => utility [patent_app_number] => 18/767939 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767939
SEMICONDUCTOR PACKAGES HAVING THERMAL CONDUCTIVE PATTERN Jul 8, 2024 Pending
Array ( [id] => 20189833 [patent_doc_number] => 12400958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Method for forming semiconductor device having an air gap between a contact pad and a sidewall of contact hole [patent_app_type] => utility [patent_app_number] => 18/743155 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 2212 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743155
Method for forming semiconductor device having an air gap between a contact pad and a sidewall of contact hole Jun 13, 2024 Issued
Array ( [id] => 19486697 [patent_doc_number] => 20240334739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/741771 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741771 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741771
Display device having a conductive metal layer disposed on a surface of an antireflection layer Jun 12, 2024 Issued
Array ( [id] => 20260554 [patent_doc_number] => 12432925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Integrated assemblies which include stacked memory decks, and methods of forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 18/735864 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 3154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735864
Integrated assemblies which include stacked memory decks, and methods of forming integrated assemblies Jun 5, 2024 Issued
Array ( [id] => 19470714 [patent_doc_number] => 20240324384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/677617 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677617 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677617
Display substrate with pixel opening areas, method for manufacturing the same, and display device May 28, 2024 Issued
Array ( [id] => 19407348 [patent_doc_number] => 20240290859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => GATE STRUCTURE IN HIGH-K METAL GATE TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 18/655397 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655397
GATE STRUCTURE IN HIGH-K METAL GATE TECHNOLOGY May 5, 2024 Pending
Array ( [id] => 19392988 [patent_doc_number] => 20240282858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => Integrated Assemblies having Transistors Configured for High-Voltage Applications, and Methods of Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 18/653289 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653289
Integrated assemblies having transistors configured for high-voltage applications, and methods of forming integrated assemblies May 1, 2024 Issued
Array ( [id] => 19363916 [patent_doc_number] => 20240265950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/635592 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635592 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635592
SEMICONDUCTOR DEVICE STRUCTURE Apr 14, 2024 Pending
Array ( [id] => 19253519 [patent_doc_number] => 20240204516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => ESD PROTECTION DEVICE WITH REDUCED HARMONIC DISTORTION [patent_app_type] => utility [patent_app_number] => 18/591681 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591681 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591681
ESD PROTECTION DEVICE WITH REDUCED HARMONIC DISTORTION Feb 28, 2024 Pending
Array ( [id] => 19337162 [patent_doc_number] => 20240251592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/583157 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583157 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583157
LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATE Feb 20, 2024 Abandoned
Array ( [id] => 19886905 [patent_doc_number] => 12272636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Interconnection structure having air gap and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/581826 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8935 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581826
Interconnection structure having air gap and method for manufacturing the same Feb 19, 2024 Issued
Array ( [id] => 19239405 [patent_doc_number] => 20240196601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/444790 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444790
Memory structure having polygonal shaped bit line contact disposed on a source/drain region Feb 18, 2024 Issued
Array ( [id] => 19981933 [patent_doc_number] => 12349435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Vertical device having a protrusion source [patent_app_type] => utility [patent_app_number] => 18/440347 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 1026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440347
Vertical device having a protrusion source Feb 12, 2024 Issued
Array ( [id] => 19936876 [patent_doc_number] => 12310097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Dielectric protection layer in middle-of-line interconnect structure manufacturing method [patent_app_type] => utility [patent_app_number] => 18/423648 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423648
Dielectric protection layer in middle-of-line interconnect structure manufacturing method Jan 25, 2024 Issued
Array ( [id] => 19191425 [patent_doc_number] => 20240170338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => VERTICAL FIELD-EFFECT TRANSISTOR DEVICES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/418795 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418795
Vertical field-effect transistor devices having gate liner Jan 21, 2024 Issued
Array ( [id] => 19928399 [patent_doc_number] => 12302711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Display device including a plurality of layers each including a light emitting layer [patent_app_type] => utility [patent_app_number] => 18/416598 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 2312 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416598
Display device including a plurality of layers each including a light emitting layer Jan 17, 2024 Issued
Array ( [id] => 19679527 [patent_doc_number] => 12191401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Manufacturing method for semiconductor structure having a plurality of fins [patent_app_type] => utility [patent_app_number] => 18/415702 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 6956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415702 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415702
Manufacturing method for semiconductor structure having a plurality of fins Jan 17, 2024 Issued
Array ( [id] => 19742891 [patent_doc_number] => 12219753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Method for fabricating a semiconductor device having a single crystal storage contact [patent_app_type] => utility [patent_app_number] => 18/538358 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538358
Method for fabricating a semiconductor device having a single crystal storage contact Dec 12, 2023 Issued
Array ( [id] => 19073469 [patent_doc_number] => 20240107895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => MAGNETORESISTIVE RANDOM ACCESS MEMORY HAVING A RING OF MAGNETIC TUNNELING JUNCTION REGION SURROUNDING AN ARRAY REGION [patent_app_type] => utility [patent_app_number] => 18/528707 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528707
Magnetoresistive random access memory having a ring of magnetic tunneling junction region surrounding an array region Dec 3, 2023 Issued
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