Search

Hoai V. Pham

Examiner (ID: 7180, Phone: (571)272-1715 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2811, 2814, 2892
Total Applications
2284
Issued Applications
2068
Pending Applications
81
Abandoned Applications
161

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20516908 [patent_doc_number] => 20260041011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => DIRECT-BONDED OPTOELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 19/353376 [patent_app_country] => US [patent_app_date] => 2025-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19353376 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/353376
DIRECT-BONDED OPTOELECTRONIC DEVICES Oct 7, 2025 Pending
Array ( [id] => 19546452 [patent_doc_number] => 20240363488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR PACKAGES HAVING THERMAL CONDUCTIVE PATTERN [patent_app_type] => utility [patent_app_number] => 18/767939 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767939
SEMICONDUCTOR PACKAGES HAVING THERMAL CONDUCTIVE PATTERN Jul 8, 2024 Pending
Array ( [id] => 19546640 [patent_doc_number] => 20240363676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT [patent_app_type] => utility [patent_app_number] => 18/767205 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767205
SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT Jul 8, 2024 Pending
Array ( [id] => 20141175 [patent_doc_number] => 20250248219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/749639 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749639 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749639
DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE Jun 20, 2024 Pending
Array ( [id] => 20189833 [patent_doc_number] => 12400958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Method for forming semiconductor device having an air gap between a contact pad and a sidewall of contact hole [patent_app_type] => utility [patent_app_number] => 18/743155 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 2212 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743155
Method for forming semiconductor device having an air gap between a contact pad and a sidewall of contact hole Jun 13, 2024 Issued
Array ( [id] => 19486697 [patent_doc_number] => 20240334739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/741771 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741771 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741771
Display device having a conductive metal layer disposed on a surface of an antireflection layer Jun 12, 2024 Issued
Array ( [id] => 20260554 [patent_doc_number] => 12432925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Integrated assemblies which include stacked memory decks, and methods of forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 18/735864 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 3154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735864
Integrated assemblies which include stacked memory decks, and methods of forming integrated assemblies Jun 5, 2024 Issued
Array ( [id] => 19470714 [patent_doc_number] => 20240324384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/677617 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677617 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677617
Display substrate with pixel opening areas, method for manufacturing the same, and display device May 28, 2024 Issued
Array ( [id] => 20369213 [patent_doc_number] => 20250359025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => MEMORY DEVICE HAVING PLANARIZED FINS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/665837 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665837 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665837
MEMORY DEVICE HAVING PLANARIZED FINS AND METHOD OF MANUFACTURING THE SAME May 15, 2024 Pending
Array ( [id] => 20352822 [patent_doc_number] => 20250349674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => SEMICONDUCTOR DIE PACKAGES AND METHODS OF FORMATION [patent_app_type] => utility [patent_app_number] => 18/657232 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657232 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657232
SEMICONDUCTOR DIE PACKAGES AND METHODS OF FORMATION May 6, 2024 Pending
Array ( [id] => 19407348 [patent_doc_number] => 20240290859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => GATE STRUCTURE IN HIGH-K METAL GATE TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 18/655397 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655397
GATE STRUCTURE IN HIGH-K METAL GATE TECHNOLOGY May 5, 2024 Pending
Array ( [id] => 19392988 [patent_doc_number] => 20240282858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => Integrated Assemblies having Transistors Configured for High-Voltage Applications, and Methods of Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 18/653289 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653289
Integrated assemblies having transistors configured for high-voltage applications, and methods of forming integrated assemblies May 1, 2024 Issued
Array ( [id] => 19363916 [patent_doc_number] => 20240265950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/635592 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635592 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635592
Semiconductor device structure having a metal layer positioned under the semiconductor substrate Apr 14, 2024 Issued
Array ( [id] => 19804046 [patent_doc_number] => 20250069971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/623293 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623293 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623293
SEMICONDUCTOR PACKAGE Mar 31, 2024 Pending
Array ( [id] => 19486684 [patent_doc_number] => 20240334726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/616522 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616522 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/616522
ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS Mar 25, 2024 Pending
Array ( [id] => 20235899 [patent_doc_number] => 20250293218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => SEMICONDUCTOR PACKAGE HAVING AN INTEGRATED PASSIVE DEVICE THAT ACTS AS A SPACER [patent_app_type] => utility [patent_app_number] => 18/606010 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606010
SEMICONDUCTOR PACKAGE HAVING AN INTEGRATED PASSIVE DEVICE THAT ACTS AS A SPACER Mar 14, 2024 Pending
Array ( [id] => 20237592 [patent_doc_number] => 20250294911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => IMAGE SENSOR PACKAGE WITH STRAY LIGHT DIRECTING MICROSTRUCTURE COMPONENT [patent_app_type] => utility [patent_app_number] => 18/605828 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605828 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/605828
IMAGE SENSOR PACKAGE WITH STRAY LIGHT DIRECTING MICROSTRUCTURE COMPONENT Mar 14, 2024 Pending
Array ( [id] => 19515770 [patent_doc_number] => 20240347456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => VERTICAL POWER SEMICONDUCTOR DEVICE COMPRISING SOURCE OR EMITTER PAD [patent_app_type] => utility [patent_app_number] => 18/606152 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606152
VERTICAL POWER SEMICONDUCTOR DEVICE COMPRISING SOURCE OR EMITTER PAD Mar 14, 2024 Pending
Array ( [id] => 19881271 [patent_doc_number] => 20250113528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => Tunnel Field Effect Transistor and Method of Fabrication Thereof [patent_app_type] => utility [patent_app_number] => 18/606175 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606175 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606175
Tunnel Field Effect Transistor and Method of Fabrication Thereof Mar 14, 2024 Pending
Array ( [id] => 19253519 [patent_doc_number] => 20240204516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => ESD PROTECTION DEVICE WITH REDUCED HARMONIC DISTORTION [patent_app_type] => utility [patent_app_number] => 18/591681 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591681 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591681
ESD protection device with reduced harmonic distortion Feb 28, 2024 Issued
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