Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19886979 [patent_doc_number] => 12272712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region [patent_app_type] => utility [patent_app_number] => 17/744664 [patent_app_country] => US [patent_app_date] => 2022-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5292 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744664
Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region May 13, 2022 Issued
Array ( [id] => 18563182 [patent_doc_number] => 11728437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor device comprising oxide semiconductor layer containing a c-axis aligned crystal [patent_app_type] => utility [patent_app_number] => 17/741698 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 52 [patent_no_of_words] => 20463 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741698 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741698
Semiconductor device comprising oxide semiconductor layer containing a c-axis aligned crystal May 10, 2022 Issued
Array ( [id] => 18985475 [patent_doc_number] => 11910688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Organic light emitting diode display substrate having band gap layer, manufacturing method thereof, and display device [patent_app_type] => utility [patent_app_number] => 17/742194 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 13482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742194
Organic light emitting diode display substrate having band gap layer, manufacturing method thereof, and display device May 10, 2022 Issued
Array ( [id] => 20118387 [patent_doc_number] => 12368105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Electronic device having a silane coupling agent in an insulating layer [patent_app_type] => utility [patent_app_number] => 17/736067 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 1171 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736067
Electronic device having a silane coupling agent in an insulating layer May 2, 2022 Issued
Array ( [id] => 19229758 [patent_doc_number] => 12009402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Method of forming a gate structure in high-k metal gate technology [patent_app_type] => utility [patent_app_number] => 17/735349 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 8110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735349 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735349
Method of forming a gate structure in high-k metal gate technology May 2, 2022 Issued
Array ( [id] => 20361864 [patent_doc_number] => 12477883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => m-LED, m-LED device, display for augmented reality or lighting applications [patent_app_type] => utility [patent_app_number] => 17/733892 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 77 [patent_figures_cnt] => 185 [patent_no_of_words] => 66333 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733892
m-LED, m-LED device, display for augmented reality or lighting applications Apr 28, 2022 Issued
Array ( [id] => 18081078 [patent_doc_number] => 20220406690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/731861 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731861
Semiconductor device having a curved part in the printed circuit board Apr 27, 2022 Issued
Array ( [id] => 18308533 [patent_doc_number] => 20230112433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/731180 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731180
Semiconductor structure including conductive layers contacting trench Apr 26, 2022 Issued
Array ( [id] => 18625645 [patent_doc_number] => 11758712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-12 [patent_title] => Manufacturing method of memory device having bit line with stepped profile [patent_app_type] => utility [patent_app_number] => 17/730065 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6341 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730065
Manufacturing method of memory device having bit line with stepped profile Apr 25, 2022 Issued
Array ( [id] => 19378251 [patent_doc_number] => 12069848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Sense line and cell contact for semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/729450 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6062 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729450
Sense line and cell contact for semiconductor devices Apr 25, 2022 Issued
Array ( [id] => 18641246 [patent_doc_number] => 11765889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Method to scale dram with self aligned bit line process [patent_app_type] => utility [patent_app_number] => 17/727907 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/727907
Method to scale dram with self aligned bit line process Apr 24, 2022 Issued
Array ( [id] => 17764917 [patent_doc_number] => 20220238530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => METHOD OF FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/659493 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/659493
Method of forming a semiconductor structure having a gate structure electrically connected to a word line Apr 17, 2022 Issued
Array ( [id] => 17764785 [patent_doc_number] => 20220238398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Methods of Forming Semiconductor Device Packages [patent_app_type] => utility [patent_app_number] => 17/722935 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722935
Method of forming semiconductor device package having testing pads on an upper die Apr 17, 2022 Issued
Array ( [id] => 17963763 [patent_doc_number] => 20220344344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES THEREIN AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/720664 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/720664
Integrated circuit devices having buried word lines therein Apr 13, 2022 Issued
Array ( [id] => 18081312 [patent_doc_number] => 20220406924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/718398 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718398 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718398
SEMICONDUCTOR DEVICE Apr 11, 2022 Abandoned
Array ( [id] => 18265165 [patent_doc_number] => 20230086407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => CONDUCTIVE PATTERN AND DISPLAY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/717554 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/717554
Conductive pattern having first and second capping layers and display device including the same Apr 10, 2022 Issued
Array ( [id] => 19155089 [patent_doc_number] => 11980025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Semiconductor device including carbon-containing contact fence [patent_app_type] => utility [patent_app_number] => 17/705991 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 9293 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705991
Semiconductor device including carbon-containing contact fence Mar 27, 2022 Issued
Array ( [id] => 18653328 [patent_doc_number] => 20230299168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => SEMICONDUCTOR DEVICE WITH CONDUCTIVE LINERS OVER SILICIDE STRUCTURES AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/695075 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695075
Semiconductor device with conductive liners over silicide structures and method of making the semiconductor device Mar 14, 2022 Issued
Array ( [id] => 17709098 [patent_doc_number] => 20220209106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => PHASE CHANGE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/695704 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695704
Phase change memory device having tapered portion of the bottom memory layer Mar 14, 2022 Issued
Array ( [id] => 18475521 [patent_doc_number] => 20230209809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHODS AND APPARATUSES OF CONTROLLING CROSS-LAYER REACTIONS IN SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/688743 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/688743
Apparatuses of controlling cross-layer reactions in semiconductor device Mar 6, 2022 Issued
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