Hoai V. Pham

Array ( [id] => 18333106 [patent_doc_number] => 11638376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Electronic device having self-aligned contacts [patent_app_type] => utility [patent_app_number] => 17/686850 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 72 [patent_no_of_words] => 11654 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18297200 [patent_doc_number] => 20230106886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => METHOD FOR MANUFACTURING MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/682770 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18601810 [patent_doc_number] => 20230276615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => MEMORY DEVICES WITH VERTICAL TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/680364 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18586124 [patent_doc_number] => 20230268389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SELF-ALIGNED BACKSIDE CONTACT INTEGRATION FOR TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/652113 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17652113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17660863 [patent_doc_number] => 20220181328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE WITH BURIED CAPACITOR AND FIN-LIKE ELECTRODES [patent_app_type] => utility [patent_app_number] => 17/676780 [patent_app_country] => US [patent_app_date] => 2022-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18999126 [patent_doc_number] => 11915982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Method of forming vertical field-effect transistor devices having gate liner [patent_app_type] => utility [patent_app_number] => 17/669452 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 6552 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17615382 [patent_doc_number] => 20220157662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SCALABLE AND FLEXIBLE ARCHITECTURES FOR INTEGRATED CIRCUIT (IC) DESIGN AND FABRICATION [patent_app_type] => utility [patent_app_number] => 17/650343 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19584148 [patent_doc_number] => 12150295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Method for manufacturing a memory using a plurality of sacrificial pillars [patent_app_type] => utility [patent_app_number] => 17/665744 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 9081 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17599475 [patent_doc_number] => 20220149049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => METHOD OF MANUFACTURING CAPACITOR CONNECTING LINE OF MEMORY AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/648464 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19185258 [patent_doc_number] => 11991876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Method for forming a semiconductor structure having second isolation structures located between adjacent active areas [patent_app_type] => utility [patent_app_number] => 17/570483 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4936 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18490296 [patent_doc_number] => 20230217650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/647346 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097561 [patent_doc_number] => 20220415902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => METHOD OF FORMING CONTACT INCLUDED IN SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/568117 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17551630 [patent_doc_number] => 20220122972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => Dummy Fins and Methods of Forming Thereof [patent_app_type] => utility [patent_app_number] => 17/567476 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168335 [patent_doc_number] => 11984246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Vertical inductor for WLCSP [patent_app_type] => utility [patent_app_number] => 17/566529 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 9508 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18509078 [patent_doc_number] => 11706914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Method of forming an array boundary structure to reduce dishing [patent_app_type] => utility [patent_app_number] => 17/555828 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 40 [patent_no_of_words] => 9715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19628794 [patent_doc_number] => 12167670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Display apparatus having thickness of the display panel in the connection area less than thickness in the pixel area [patent_app_type] => utility [patent_app_number] => 17/545078 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 21258 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18403726 [patent_doc_number] => 11665886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Method for fabricating semiconductor device with carbon liner over gate structure [patent_app_type] => utility [patent_app_number] => 17/544676 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7799 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17486105 [patent_doc_number] => 20220093609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH POROUS DECOUPLING FEATURES [patent_app_type] => utility [patent_app_number] => 17/537955 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18317530 [patent_doc_number] => 11631614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => MIM capacitor with adjustable capacitance via electronic fuses [patent_app_type] => utility [patent_app_number] => 17/536464 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5397 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19495742 [patent_doc_number] => 12114481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Method for manufacturing semiconductor structure having conductive block connected to transistor on the substrate [patent_app_type] => utility [patent_app_number] => 17/456480 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 5612 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456480 [rel_patent_id] =>[rel_patent_doc_number] =>)