Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18841501 [patent_doc_number] => 11849598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Organic light-emitting component having a light-emitting layer as part of a charge generation layer [patent_app_type] => utility [patent_app_number] => 17/531249 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4985 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531249
Organic light-emitting component having a light-emitting layer as part of a charge generation layer Nov 18, 2021 Issued
Array ( [id] => 18646834 [patent_doc_number] => 11770926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Semiconductor devices including an edge insulating layer [patent_app_type] => utility [patent_app_number] => 17/530818 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 39 [patent_no_of_words] => 9425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530818
Semiconductor devices including an edge insulating layer Nov 18, 2021 Issued
Array ( [id] => 18783885 [patent_doc_number] => 11825692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Organic light emitting display panel including a plurality organic and inorganic layers [patent_app_type] => utility [patent_app_number] => 17/526864 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8077 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526864
Organic light emitting display panel including a plurality organic and inorganic layers Nov 14, 2021 Issued
Array ( [id] => 19378253 [patent_doc_number] => 12069850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Semiconductor structure, manufacturing method thereof, and memory having bit line conducting layers covering the bit line contact layer and the insulating layer [patent_app_type] => utility [patent_app_number] => 17/523084 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523084
Semiconductor structure, manufacturing method thereof, and memory having bit line conducting layers covering the bit line contact layer and the insulating layer Nov 9, 2021 Issued
Array ( [id] => 17448430 [patent_doc_number] => 20220068935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => GAP FILL METHODS FOR DRAM [patent_app_type] => utility [patent_app_number] => 17/522448 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522448
Method of testing a gap fill for DRAM Nov 8, 2021 Issued
Array ( [id] => 17963766 [patent_doc_number] => 20220344347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/520868 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520868
Method for manufacturing a semiconductor device using a support layer to form a gate structure Nov 7, 2021 Issued
Array ( [id] => 17630653 [patent_doc_number] => 20220165668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR PREPARING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/521849 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521849
Semiconductor device having an air gap between a contact pad and a sidewall of contact hole Nov 7, 2021 Issued
Array ( [id] => 17431700 [patent_doc_number] => 20220059409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/518614 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518614 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518614
Semiconductor device having plurality of insulators Nov 3, 2021 Issued
Array ( [id] => 19229665 [patent_doc_number] => 12009309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Semiconductor device having a plurality of semiconductor layers covering an emission layer [patent_app_type] => utility [patent_app_number] => 17/517955 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 10228 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517955
Semiconductor device having a plurality of semiconductor layers covering an emission layer Nov 2, 2021 Issued
Array ( [id] => 18464415 [patent_doc_number] => 11688711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Semiconductor device having second connector that overlaps a part of first connector [patent_app_type] => utility [patent_app_number] => 17/516019 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7570 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516019
Semiconductor device having second connector that overlaps a part of first connector Oct 31, 2021 Issued
Array ( [id] => 19023183 [patent_doc_number] => 20240079354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => SUBSTRATE INTEGRATED WITH PASSIVE DEVICE, AND PRODUCTION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/271117 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18271117 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/271117
SUBSTRATE INTEGRATED WITH PASSIVE DEVICE, AND PRODUCTION METHOD THEREFOR Oct 28, 2021 Pending
Array ( [id] => 18139817 [patent_doc_number] => 20230013653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => MEMORY DEVICE AND METHOD FOR FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/512903 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512903
MEMORY DEVICE AND METHOD FOR FORMING SAME Oct 27, 2021 Abandoned
Array ( [id] => 19446351 [patent_doc_number] => 12096665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Display device having a sensor disposed under the display panel [patent_app_type] => utility [patent_app_number] => 17/512396 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 14248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512396
Display device having a sensor disposed under the display panel Oct 26, 2021 Issued
Array ( [id] => 18326587 [patent_doc_number] => 20230124715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => MEMORY STRUCTURE HAVING A HEXAGONAL SHAPED BIT LINE CONTACT DISPOSED ON A SOURCE/DRAIN REGION [patent_app_type] => utility [patent_app_number] => 17/451157 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451157
Memory structure having a hexagonal shaped bit line contact disposed on a source/drain region Oct 17, 2021 Issued
Array ( [id] => 19704973 [patent_doc_number] => 12199020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Integrated power switching device heat sink [patent_app_type] => utility [patent_app_number] => 17/503433 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 45 [patent_no_of_words] => 4972 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17503433 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/503433
Integrated power switching device heat sink Oct 17, 2021 Issued
Array ( [id] => 18325524 [patent_doc_number] => 20230123652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDCUTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/450833 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450833
Method of forming a semicondcutor device using carbon containing spacer for a bitline Oct 13, 2021 Issued
Array ( [id] => 17373811 [patent_doc_number] => 20220028863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => METHOD FOR MANUFACTURING A CAPACITIVE ELEMENT, AND CORRESPONDING INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/493226 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493226
Capacitive element comprising a monolithic conductive region having one part covering a front surface of a substrate and at least one part extending into an active region perpendicularly to the front surface Oct 3, 2021 Issued
Array ( [id] => 19460143 [patent_doc_number] => 12100650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Semiconductor device having a carbon containing insulation layer formed under the source/drain [patent_app_type] => utility [patent_app_number] => 17/491716 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8906 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491716
Semiconductor device having a carbon containing insulation layer formed under the source/drain Sep 30, 2021 Issued
Array ( [id] => 18297679 [patent_doc_number] => 20230107365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => METHODS FOR FORMING OPENINGS IN CONDUCTIVE LAYERS AND USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/491825 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491825
Methods for forming openings in conductive layers and using the same Sep 30, 2021 Issued
Array ( [id] => 18688361 [patent_doc_number] => 11784104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Method of forming electronic chip package having a conductive layer between a chip and a support [patent_app_type] => utility [patent_app_number] => 17/491189 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2333 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491189
Method of forming electronic chip package having a conductive layer between a chip and a support Sep 29, 2021 Issued
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