Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18016405 [patent_doc_number] => 11508712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Method of manufacturing a package-on-package type semiconductor package [patent_app_type] => utility [patent_app_number] => 17/120991 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120991
Method of manufacturing a package-on-package type semiconductor package Dec 13, 2020 Issued
Array ( [id] => 18048185 [patent_doc_number] => 11522143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Display device having a circuit board connected to a signal line by a conductive material in a substrate [patent_app_type] => utility [patent_app_number] => 17/114732 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 17075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114732
Display device having a circuit board connected to a signal line by a conductive material in a substrate Dec 7, 2020 Issued
Array ( [id] => 16781967 [patent_doc_number] => 20210119046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => FinFET Structure and Method with Reduced Fin Buckling [patent_app_type] => utility [patent_app_number] => 17/113955 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113955
FinFET structure and method with reduced fin buckling Dec 6, 2020 Issued
Array ( [id] => 17745731 [patent_doc_number] => 11393813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Method of architecture design for enhanced 3D device performance [patent_app_type] => utility [patent_app_number] => 17/113736 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 7923 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113736
Method of architecture design for enhanced 3D device performance Dec 6, 2020 Issued
Array ( [id] => 16781665 [patent_doc_number] => 20210118744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => Using a Metal-Containing Layer as an Etching Stop Layer and to Pattern Source/Drain Regions of a FinFET [patent_app_type] => utility [patent_app_number] => 17/111978 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111978
Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET Dec 3, 2020 Issued
Array ( [id] => 18112787 [patent_doc_number] => 20230005667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/784857 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17784857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/784857
Electronic component having the dielectric film not covers a corner part of the lower electrode Dec 3, 2020 Issued
Array ( [id] => 16724078 [patent_doc_number] => 20210091225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/110603 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110603
Semiconductor device comprising first and second insulating layer each has a tapered shape Dec 2, 2020 Issued
Array ( [id] => 16765704 [patent_doc_number] => 20210111286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => MULTI-WELL SELENIUM DEVICE AND METHOD FOR FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/108094 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108094 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108094
Multi-well selenium device and method for fabrication thereof Nov 30, 2020 Issued
Array ( [id] => 16966224 [patent_doc_number] => 20210217723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/108486 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108486
Semiconductor device and method for manufacturing semiconductor device having first and second wires in different diameter Nov 30, 2020 Issued
Array ( [id] => 16716066 [patent_doc_number] => 20210083213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/107320 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107320
DISPLAY APPARATUS Nov 29, 2020 Abandoned
Array ( [id] => 17645118 [patent_doc_number] => 20220172857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => ENHANCED GRATING ALIGNED PATTERNING FOR EUV DIRECT PRINT PROCESSES [patent_app_type] => utility [patent_app_number] => 17/107717 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107717
Enhanced grating aligned patterning for EUV direct print processes Nov 29, 2020 Issued
Array ( [id] => 17463697 [patent_doc_number] => 20220077003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => METHOD FOR FABRICATING A 3D SEMICONDUCTOR APPARATUS HAVING TWO VERTICALLY DISPOSED SEMINCONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/951125 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951125
Method for fabricating a 3D semiconductor apparatus having two vertically disposed seminconductor devices Nov 17, 2020 Issued
Array ( [id] => 16692434 [patent_doc_number] => 20210074913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => PHASE CHANGE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/950753 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950753 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950753
Phase change memory device having tapered portion of the bottom memory layer Nov 16, 2020 Issued
Array ( [id] => 18113237 [patent_doc_number] => 20230006117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => ELECTRONIC PART AND METHOD OF PRODUCING ELECTRONIC PART [patent_app_type] => utility [patent_app_number] => 17/756476 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17756476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/756476
ELECTRONIC PART AND METHOD OF PRODUCING ELECTRONIC PART Nov 12, 2020 Abandoned
Array ( [id] => 16858689 [patent_doc_number] => 20210159434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/095943 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095943 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095943
Foldable electronic device having an elastic body in openings of the spacers Nov 11, 2020 Issued
Array ( [id] => 18999275 [patent_doc_number] => 11916131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Vertical device having a protrusion source [patent_app_type] => utility [patent_app_number] => 17/088749 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 5755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088749
Vertical device having a protrusion source Nov 3, 2020 Issued
Array ( [id] => 16617503 [patent_doc_number] => 20210036156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => METHOD TO INDUCE STRAIN IN 3-D MICROFABRICATED STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/074121 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074121
Method to induce strain in 3-D microfabricated structures Oct 18, 2020 Issued
Array ( [id] => 17803060 [patent_doc_number] => 11417369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Semiconductor device structure with an underground interconnection embedded into a silicon substrate [patent_app_type] => utility [patent_app_number] => 17/065543 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 9971 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065543
Semiconductor device structure with an underground interconnection embedded into a silicon substrate Oct 7, 2020 Issued
Array ( [id] => 17493439 [patent_doc_number] => 11282752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Method of forming vertical field-effect transistor devices having gate liner [patent_app_type] => utility [patent_app_number] => 17/035857 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 6537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035857
Method of forming vertical field-effect transistor devices having gate liner Sep 28, 2020 Issued
Array ( [id] => 17683445 [patent_doc_number] => 11367710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Multi-chip package structure having dummy pad disposed between input/output units [patent_app_type] => utility [patent_app_number] => 17/034161 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3803 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034161
Multi-chip package structure having dummy pad disposed between input/output units Sep 27, 2020 Issued
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