Search

Hoai V. Pham

Examiner (ID: 7180, Phone: (571)272-1715 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2811, 2814, 2892
Total Applications
2284
Issued Applications
2068
Pending Applications
81
Abandoned Applications
161

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17417151 [patent_doc_number] => 20220052055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/152360 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152360 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152360
Method for fabricating a semiconductor device having a trench exposing a sidewall of the contact plug aligned with the sidewall of the substrate Jan 18, 2021 Issued
Array ( [id] => 17847983 [patent_doc_number] => 11437369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Array of multi-stack nanosheet structures [patent_app_type] => utility [patent_app_number] => 17/147587 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 8017 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147587 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147587
Array of multi-stack nanosheet structures Jan 12, 2021 Issued
Array ( [id] => 18943631 [patent_doc_number] => 20240038770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => DISPLAY PANEL AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/271231 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17271231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/271231
DISPLAY PANEL AND METHOD OF MANUFACTURING SAME Dec 29, 2020 Pending
Array ( [id] => 18032174 [patent_doc_number] => 11515374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Display device including a plurality of layers each including a light emitting layer and having an island shape [patent_app_type] => utility [patent_app_number] => 17/135926 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6993 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135926
Display device including a plurality of layers each including a light emitting layer and having an island shape Dec 27, 2020 Issued
Array ( [id] => 17956412 [patent_doc_number] => 11482525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Method for manufacturing semiconductor structure with capacitor landing pad [patent_app_type] => utility [patent_app_number] => 17/129063 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6355 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129063 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129063
Method for manufacturing semiconductor structure with capacitor landing pad Dec 20, 2020 Issued
Array ( [id] => 17692178 [patent_doc_number] => 20220199471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => Multi-Transistor Stack Architecture [patent_app_type] => utility [patent_app_number] => 17/125700 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125700
Method of forming multi-stack transistors in a single semiconductor die Dec 16, 2020 Issued
Array ( [id] => 18016405 [patent_doc_number] => 11508712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Method of manufacturing a package-on-package type semiconductor package [patent_app_type] => utility [patent_app_number] => 17/120991 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120991
Method of manufacturing a package-on-package type semiconductor package Dec 13, 2020 Issued
Array ( [id] => 18048185 [patent_doc_number] => 11522143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Display device having a circuit board connected to a signal line by a conductive material in a substrate [patent_app_type] => utility [patent_app_number] => 17/114732 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 17075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114732
Display device having a circuit board connected to a signal line by a conductive material in a substrate Dec 7, 2020 Issued
Array ( [id] => 16781967 [patent_doc_number] => 20210119046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => FinFET Structure and Method with Reduced Fin Buckling [patent_app_type] => utility [patent_app_number] => 17/113955 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113955
FinFET structure and method with reduced fin buckling Dec 6, 2020 Issued
Array ( [id] => 17745731 [patent_doc_number] => 11393813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Method of architecture design for enhanced 3D device performance [patent_app_type] => utility [patent_app_number] => 17/113736 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 7923 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113736
Method of architecture design for enhanced 3D device performance Dec 6, 2020 Issued
Array ( [id] => 16781665 [patent_doc_number] => 20210118744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => Using a Metal-Containing Layer as an Etching Stop Layer and to Pattern Source/Drain Regions of a FinFET [patent_app_type] => utility [patent_app_number] => 17/111978 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7651 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111978
Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET Dec 3, 2020 Issued
Array ( [id] => 18112787 [patent_doc_number] => 20230005667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/784857 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17784857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/784857
Electronic component having the dielectric film not covers a corner part of the lower electrode Dec 3, 2020 Issued
Array ( [id] => 16724078 [patent_doc_number] => 20210091225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/110603 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110603
Semiconductor device comprising first and second insulating layer each has a tapered shape Dec 2, 2020 Issued
Array ( [id] => 16966224 [patent_doc_number] => 20210217723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/108486 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108486
Semiconductor device and method for manufacturing semiconductor device having first and second wires in different diameter Nov 30, 2020 Issued
Array ( [id] => 16765704 [patent_doc_number] => 20210111286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => MULTI-WELL SELENIUM DEVICE AND METHOD FOR FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/108094 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108094 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108094
Multi-well selenium device and method for fabrication thereof Nov 30, 2020 Issued
Array ( [id] => 16716066 [patent_doc_number] => 20210083213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/107320 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107320
DISPLAY APPARATUS Nov 29, 2020 Abandoned
Array ( [id] => 17645118 [patent_doc_number] => 20220172857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => ENHANCED GRATING ALIGNED PATTERNING FOR EUV DIRECT PRINT PROCESSES [patent_app_type] => utility [patent_app_number] => 17/107717 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107717
Enhanced grating aligned patterning for EUV direct print processes Nov 29, 2020 Issued
Array ( [id] => 17463697 [patent_doc_number] => 20220077003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => METHOD FOR FABRICATING A 3D SEMICONDUCTOR APPARATUS HAVING TWO VERTICALLY DISPOSED SEMINCONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/951125 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951125
Method for fabricating a 3D semiconductor apparatus having two vertically disposed seminconductor devices Nov 17, 2020 Issued
Array ( [id] => 16692434 [patent_doc_number] => 20210074913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => PHASE CHANGE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/950753 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950753 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950753
Phase change memory device having tapered portion of the bottom memory layer Nov 16, 2020 Issued
Array ( [id] => 18113237 [patent_doc_number] => 20230006117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => ELECTRONIC PART AND METHOD OF PRODUCING ELECTRONIC PART [patent_app_type] => utility [patent_app_number] => 17/756476 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17756476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/756476
ELECTRONIC PART AND METHOD OF PRODUCING ELECTRONIC PART Nov 12, 2020 Abandoned
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