Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17456050 [patent_doc_number] => 11270917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Scalable and flexible architectures for integrated circuit (IC) design and fabrication [patent_app_type] => utility [patent_app_number] => 16/889304 [patent_app_country] => US [patent_app_date] => 2020-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 15656 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889304 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889304
Scalable and flexible architectures for integrated circuit (IC) design and fabrication May 31, 2020 Issued
Array ( [id] => 17262896 [patent_doc_number] => 20210375881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR DEVICE WITH POROUS DECOUPLING FEATURE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/885825 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885825
Semiconductor device with porous decoupling feature May 27, 2020 Issued
Array ( [id] => 16803450 [patent_doc_number] => 10998406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Silicon carbide single crystal substrate, silicon carbide epitaxial substrate, and method of manufacturing silicon carbide semiconductor device [patent_app_type] => utility [patent_app_number] => 16/882153 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 9264 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882153
Silicon carbide single crystal substrate, silicon carbide epitaxial substrate, and method of manufacturing silicon carbide semiconductor device May 21, 2020 Issued
Array ( [id] => 16286235 [patent_doc_number] => 20200279837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => Semiconductor Devices and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/876471 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876471 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876471
Methods of bonding the strip-shaped under bump metallization structures May 17, 2020 Issued
Array ( [id] => 17544078 [patent_doc_number] => 11309211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Method for forming semiconductor device with buried gate structure [patent_app_type] => utility [patent_app_number] => 16/874223 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874223
Method for forming semiconductor device with buried gate structure May 13, 2020 Issued
Array ( [id] => 16471771 [patent_doc_number] => 20200373309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => METHODS OF FORMING SELF-ALIGNED CONTACTS [patent_app_type] => utility [patent_app_number] => 16/868933 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868933 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868933
Methods of forming self-aligned contacts comprising reusing hardmask materials and lithography reticles May 6, 2020 Issued
Array ( [id] => 16256879 [patent_doc_number] => 20200266254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/866444 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866444 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866444
Organic light emitting display panel including a plurality organic and inorganic layers May 3, 2020 Issued
Array ( [id] => 17714629 [patent_doc_number] => 11378618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Method for manufacturing electronic device having a seed layer on a substrate [patent_app_type] => utility [patent_app_number] => 16/861230 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861230 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861230
Method for manufacturing electronic device having a seed layer on a substrate Apr 28, 2020 Issued
Array ( [id] => 16904790 [patent_doc_number] => 20210183706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/861823 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861823 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861823
Method of forming a semiconductor structure by sacrificial layers and spacer Apr 28, 2020 Issued
Array ( [id] => 16716072 [patent_doc_number] => 20210083219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => DISPLAY SUBSTRATE AND PREPARATION METHOD THEREOF, DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/853097 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853097 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/853097
Display substrate having pixel definition layer comprises a lyophilic and lyophobic materials Apr 19, 2020 Issued
Array ( [id] => 16210543 [patent_doc_number] => 20200243533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => MEMORY TRANSISTOR, FABRICATION METHOD THEREOF AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/849217 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849217 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/849217
Memory transistor with cavity structure Apr 14, 2020 Issued
Array ( [id] => 16865908 [patent_doc_number] => 11024661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Solid-state image pickup device having pixel separation wall [patent_app_type] => utility [patent_app_number] => 16/849866 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 21591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/849866
Solid-state image pickup device having pixel separation wall Apr 14, 2020 Issued
Array ( [id] => 18137374 [patent_doc_number] => 11563063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => OLED display substrate comprising camera and protective layer, fabricating method thereof, and display device [patent_app_type] => utility [patent_app_number] => 16/848151 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4083 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16848151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/848151
OLED display substrate comprising camera and protective layer, fabricating method thereof, and display device Apr 13, 2020 Issued
Array ( [id] => 16502800 [patent_doc_number] => 10868202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Method for fabrication a multi-well amorphous selenium detector [patent_app_type] => utility [patent_app_number] => 16/845471 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 4792 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845471 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845471
Method for fabrication a multi-well amorphous selenium detector Apr 9, 2020 Issued
Array ( [id] => 16194110 [patent_doc_number] => 20200234959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => Methods And Materials For Modifying The Threshold Voltage Of Metal Oxide Stacks [patent_app_type] => utility [patent_app_number] => 16/841625 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/841625
Methods and materials for modifying the threshold voltage of metal oxide stacks Apr 5, 2020 Issued
Array ( [id] => 16194236 [patent_doc_number] => 20200235085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => DIRECT-BONDED LED ARRAYS AND APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/840245 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840245 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840245
Direct-bonded LED structure contacts and substrate contacts Apr 2, 2020 Issued
Array ( [id] => 17326561 [patent_doc_number] => 11217586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Semiconductor device having dummy fin physically separating the first and second gate stacks [patent_app_type] => utility [patent_app_number] => 16/837563 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 62 [patent_no_of_words] => 13135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837563 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/837563
Semiconductor device having dummy fin physically separating the first and second gate stacks Mar 31, 2020 Issued
Array ( [id] => 17284052 [patent_doc_number] => 11201093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Method of manufacturing a semiconductor device including the horizontal channel FET and the vertical channel FET [patent_app_type] => utility [patent_app_number] => 16/836653 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 8828 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836653
Method of manufacturing a semiconductor device including the horizontal channel FET and the vertical channel FET Mar 30, 2020 Issued
Array ( [id] => 17692589 [patent_doc_number] => 20220199882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => LIGHT EMITTING DIODE CHIP-SCALE PACKAGE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/600403 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17600403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/600403
LIGHT EMITTING DIODE CHIP-SCALE PACKAGE AND METHOD FOR MANUFACTURING SAME Mar 25, 2020 Pending
Array ( [id] => 17692589 [patent_doc_number] => 20220199882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => LIGHT EMITTING DIODE CHIP-SCALE PACKAGE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/600403 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17600403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/600403
LIGHT EMITTING DIODE CHIP-SCALE PACKAGE AND METHOD FOR MANUFACTURING SAME Mar 25, 2020 Pending
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