Search

Hoai V. Pham

Examiner (ID: 7180, Phone: (571)272-1715 , Office: P/2892 )

Most Active Art Unit
2892
Art Unit(s)
2811, 2814, 2892
Total Applications
2284
Issued Applications
2068
Pending Applications
81
Abandoned Applications
161

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19337162 [patent_doc_number] => 20240251592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/583157 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583157 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583157
LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATE Feb 20, 2024 Abandoned
Array ( [id] => 19886905 [patent_doc_number] => 12272636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Interconnection structure having air gap and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/581826 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8935 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581826
Interconnection structure having air gap and method for manufacturing the same Feb 19, 2024 Issued
Array ( [id] => 19239405 [patent_doc_number] => 20240196601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/444790 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444790
Memory structure having polygonal shaped bit line contact disposed on a source/drain region Feb 18, 2024 Issued
Array ( [id] => 19981933 [patent_doc_number] => 12349435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Vertical device having a protrusion source [patent_app_type] => utility [patent_app_number] => 18/440347 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 1026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440347
Vertical device having a protrusion source Feb 12, 2024 Issued
Array ( [id] => 19384710 [patent_doc_number] => 20240274580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => TERRACED SUPPORT STRUCTURE TO MITIGATE STACKED DIE OVERHANG DEFLECTION [patent_app_type] => utility [patent_app_number] => 18/433911 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433911 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433911
TERRACED SUPPORT STRUCTURE TO MITIGATE STACKED DIE OVERHANG DEFLECTION Feb 5, 2024 Pending
Array ( [id] => 19936876 [patent_doc_number] => 12310097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Dielectric protection layer in middle-of-line interconnect structure manufacturing method [patent_app_type] => utility [patent_app_number] => 18/423648 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423648
Dielectric protection layer in middle-of-line interconnect structure manufacturing method Jan 25, 2024 Issued
Array ( [id] => 19191425 [patent_doc_number] => 20240170338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => VERTICAL FIELD-EFFECT TRANSISTOR DEVICES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/418795 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418795
Vertical field-effect transistor devices having gate liner Jan 21, 2024 Issued
Array ( [id] => 19928399 [patent_doc_number] => 12302711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Display device including a plurality of layers each including a light emitting layer [patent_app_type] => utility [patent_app_number] => 18/416598 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 2312 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416598
Display device including a plurality of layers each including a light emitting layer Jan 17, 2024 Issued
Array ( [id] => 19679527 [patent_doc_number] => 12191401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Manufacturing method for semiconductor structure having a plurality of fins [patent_app_type] => utility [patent_app_number] => 18/415702 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 6956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415702 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415702
Manufacturing method for semiconductor structure having a plurality of fins Jan 17, 2024 Issued
Array ( [id] => 20898856 [patent_doc_number] => 12706124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-11 [patent_title] => Semiconductor device structure [patent_app_type] => utility [patent_app_number] => 18/408510 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 6282 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408510 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408510
SEMICONDUCTOR DEVICE STRUCTURE Jan 8, 2024 Pending
Array ( [id] => 19835864 [patent_doc_number] => 20250087650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 18/396809 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396809 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/396809
DISPLAY PANEL Dec 26, 2023 Pending
Array ( [id] => 20962775 [patent_doc_number] => 12733230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-08 [patent_title] => Method for fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 18/538469 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 1123 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538469
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Dec 12, 2023 Pending
Array ( [id] => 19742891 [patent_doc_number] => 12219753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Method for fabricating a semiconductor device having a single crystal storage contact [patent_app_type] => utility [patent_app_number] => 18/538358 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538358
Method for fabricating a semiconductor device having a single crystal storage contact Dec 12, 2023 Issued
Array ( [id] => 19253024 [patent_doc_number] => 20240204021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => POLARIMETRIC IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 18/537928 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537928
POLARIMETRIC IMAGE SENSOR Dec 12, 2023 Pending
Array ( [id] => 20019646 [patent_doc_number] => 20250157868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/533191 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533191 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533191
SEMICONDUCTOR STRUCTURE Dec 7, 2023 Pending
Array ( [id] => 19073469 [patent_doc_number] => 20240107895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => MAGNETORESISTIVE RANDOM ACCESS MEMORY HAVING A RING OF MAGNETIC TUNNELING JUNCTION REGION SURROUNDING AN ARRAY REGION [patent_app_type] => utility [patent_app_number] => 18/528707 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528707
Magnetoresistive random access memory having a ring of magnetic tunneling junction region surrounding an array region Dec 3, 2023 Issued
Array ( [id] => 19721898 [patent_doc_number] => 12207456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Method of forming an integrated circuit devices having buried word lines [patent_app_type] => utility [patent_app_number] => 18/525187 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525187
Method of forming an integrated circuit devices having buried word lines Nov 29, 2023 Issued
Array ( [id] => 19057017 [patent_doc_number] => 20240098986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => METHOD OF FORMING CONTACT INCLUDED IN SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/524794 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524794
Method of forming contact included in semiconductor device Nov 29, 2023 Issued
Array ( [id] => 19928300 [patent_doc_number] => 12302611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => FinFET structure with a composite stress layer and reduced fin buckling [patent_app_type] => utility [patent_app_number] => 18/521584 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521584
FinFET structure with a composite stress layer and reduced fin buckling Nov 27, 2023 Issued
Array ( [id] => 20869686 [patent_doc_number] => 12696603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-28 [patent_title] => LED support, preparation method thereof, and device [patent_app_type] => utility [patent_app_number] => 18/516594 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516594 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516594
LED SUPPORT, PREPARATION METHOD THEREOF, AND DEVICE Nov 20, 2023 Issued
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