Hoai V. Pham

Array ( [id] => 17002724 [patent_doc_number] => 11081547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Method for making superimposed transistors [patent_app_type] => utility [patent_app_number] => 16/580396 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 6707 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15718051 [patent_doc_number] => 20200105793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/580320 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17092887 [patent_doc_number] => 11121085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Trench walls, conductive structures having different widths and methods of making same [patent_app_type] => utility [patent_app_number] => 16/580450 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3290 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16959068 [patent_doc_number] => 11062949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Method of manufacturing power device with improved the utilization rate of wafer area [patent_app_type] => utility [patent_app_number] => 16/580273 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3584 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16226449 [patent_doc_number] => 20200251566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => GATE STRUCTURE IN HIGH-K METAL GATE TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 16/580296 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16723894 [patent_doc_number] => 20210091041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => THREE-DIMENSIONAL INTEGRATED CIRCUIT TEST AND IMPROVED THERMAL DISSIPATION [patent_app_type] => utility [patent_app_number] => 16/580349 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16173044 [patent_doc_number] => 10714624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Thin-film transistor fabrication method for reducing size of thin-film transistor and pixel area [patent_app_type] => utility [patent_app_number] => 16/579708 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4807 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16579708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15657219 [patent_doc_number] => 20200091140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => SEMICONDUCTOR UNIT, SEMICONDUCTOR MODULE, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/566579 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17048227 [patent_doc_number] => 11101418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-24 [patent_title] => Spacer for self-aligned mesa [patent_app_type] => utility [patent_app_number] => 16/566750 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8578 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15969719 [patent_doc_number] => 20200168611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/566510 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17078086 [patent_doc_number] => 11114502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Resistive memory cell having an ovonic threshold switch [patent_app_type] => utility [patent_app_number] => 16/566794 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3589 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16865804 [patent_doc_number] => 11024557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Semiconductor package structure having vapor chamber thermally connected to a surface of the semiconductor die [patent_app_type] => utility [patent_app_number] => 16/566495 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15625477 [patent_doc_number] => 20200083143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/566502 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16739215 [patent_doc_number] => 10964884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Magnetic memory device having an incline side surface [patent_app_type] => utility [patent_app_number] => 16/566557 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4138 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16803445 [patent_doc_number] => 10998401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Semiconductor device having a base body of silicon carbide [patent_app_type] => utility [patent_app_number] => 16/566555 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 11626 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17018494 [patent_doc_number] => 11088140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Multiple semiconductor elements with different threshold voltages [patent_app_type] => utility [patent_app_number] => 16/552260 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 10702 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16609376 [patent_doc_number] => 10910391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Semiconductor memory device having a plurality of first semiconductor films [patent_app_type] => utility [patent_app_number] => 16/552255 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 64 [patent_no_of_words] => 10871 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16820123 [patent_doc_number] => 11004962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Integrated circuit including at least one nano-ridge transistor [patent_app_type] => utility [patent_app_number] => 16/552468 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 7803 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17078128 [patent_doc_number] => 11114544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Integrated circuit device having fin-type active [patent_app_type] => utility [patent_app_number] => 16/552150 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11002 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17978898 [patent_doc_number] => 11495775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Light-emitting device including encapsulation layers having different refractive indexes, method of manufacturing the same and electronic apparatus [patent_app_type] => utility [patent_app_number] => 16/959400 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 11358 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16959400 [rel_patent_id] =>[rel_patent_doc_number] =>)