Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15260383 [patent_doc_number] => 20190378925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/432615 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432615
Semiconductor device having a drain drift-region in contact with the body region Jun 4, 2019 Issued
Array ( [id] => 16645560 [patent_doc_number] => 10923428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Semiconductor package having second pad electrically connected through the interposer chip to the first pad [patent_app_type] => utility [patent_app_number] => 16/432551 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 8297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432551 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432551
Semiconductor package having second pad electrically connected through the interposer chip to the first pad Jun 4, 2019 Issued
Array ( [id] => 15274235 [patent_doc_number] => 20190385852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => Semiconductor Device and Method of Manufacturing a Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/432211 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432211 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432211
Method of manufacturing a semiconductor device by using ion beam technique Jun 4, 2019 Issued
Array ( [id] => 14938307 [patent_doc_number] => 20190304792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Interconnect Structure and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/429179 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429179 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/429179
Interconnect structure having a carbon-containing barrier layer Jun 2, 2019 Issued
Array ( [id] => 15000315 [patent_doc_number] => 20190319115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => BIPOLAR TRANSISTOR WITH TRENCH STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/427356 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/427356
Method of manufacturing a bipolar transistor with trench structure May 30, 2019 Issued
Array ( [id] => 17319401 [patent_doc_number] => 20210408451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => ORGANIC LIGHT EMITTING DIODE AND METHOD OF FABRICATING THEREOF [patent_app_type] => utility [patent_app_number] => 16/481096 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16481096 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/481096
Organic light emitting diode comprising inverted triangular groove structure at boundary line between display region and non-display region and method of fabricating thereof May 19, 2019 Issued
Array ( [id] => 14969127 [patent_doc_number] => 20190312042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING SILICON/GERMANIUM ACTIVE REGIONS WITH DIFFERENT GERMANIUM CONCENTRATIONS [patent_app_type] => utility [patent_app_number] => 16/416477 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416477
Semiconductor devices having silicon/germanium active regions with different germanium concentrations May 19, 2019 Issued
Array ( [id] => 14813027 [patent_doc_number] => 20190273123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/416044 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416044 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416044
Method of manufacturing a display device utilizing pixel and dummy portions May 16, 2019 Issued
Array ( [id] => 16456225 [patent_doc_number] => 20200365651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => DEVICE COMPRISING SUBTRATE AND DIE WITH FRAME [patent_app_type] => utility [patent_app_number] => 16/414572 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414572 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414572
DEVICE COMPRISING SUBTRATE AND DIE WITH FRAME May 15, 2019 Abandoned
Array ( [id] => 15370085 [patent_doc_number] => 20200020807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => FinFET Structure and Method with Reduced Fin Buckling [patent_app_type] => utility [patent_app_number] => 16/414565 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414565
Method of forming FinFET structure with reduced Fin buckling May 15, 2019 Issued
Array ( [id] => 16464351 [patent_doc_number] => 10847716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-24 [patent_title] => Method for manufacturing a phase change memory device having a second opening above a first opening in the dielectric layer [patent_app_type] => utility [patent_app_number] => 16/414582 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 10915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414582 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414582
Method for manufacturing a phase change memory device having a second opening above a first opening in the dielectric layer May 15, 2019 Issued
Array ( [id] => 16210603 [patent_doc_number] => 20200243593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => CMOS IMAGE SENSOR WITH COMPACT PIXEL LAYOUT [patent_app_type] => utility [patent_app_number] => 16/414669 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414669
CMOS image sensor with compact pixel layout May 15, 2019 Issued
Array ( [id] => 16593813 [patent_doc_number] => 10903090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Method of singulate a package structure using a light transmitting film on a polymer layer [patent_app_type] => utility [patent_app_number] => 16/414763 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414763 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414763
Method of singulate a package structure using a light transmitting film on a polymer layer May 15, 2019 Issued
Array ( [id] => 17122147 [patent_doc_number] => 11133289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Semiconductor package and manufacturing method of semiconductor package having plurality of encapsulating materials [patent_app_type] => utility [patent_app_number] => 16/414723 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 14676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414723 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414723
Semiconductor package and manufacturing method of semiconductor package having plurality of encapsulating materials May 15, 2019 Issued
Array ( [id] => 14969085 [patent_doc_number] => 20190312021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => Method of Manufacturing a Package-on-Package Type Semiconductor Package [patent_app_type] => utility [patent_app_number] => 16/412166 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412166
Method of manufacturing a package-on-package type semiconductor package May 13, 2019 Issued
Array ( [id] => 14813143 [patent_doc_number] => 20190273181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => VERTICAL TYPE LIGHT EMITTING DIODE [patent_app_type] => utility [patent_app_number] => 16/409603 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16409603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/409603
Vertical type light emitting diode having groove disposed under the first conductivity type semiconductor layer May 9, 2019 Issued
Array ( [id] => 14785265 [patent_doc_number] => 20190267530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/405651 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/405651
Light emitting device having a pair of vias passing through a center of the concave component May 6, 2019 Issued
Array ( [id] => 15401449 [patent_doc_number] => 10541388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Method for fabricating a display device are capable of substantially minimizing damage and carbonization of a substrate [patent_app_type] => utility [patent_app_number] => 16/404512 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 10638 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404512 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404512
Method for fabricating a display device are capable of substantially minimizing damage and carbonization of a substrate May 5, 2019 Issued
Array ( [id] => 16048307 [patent_doc_number] => 10686039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end [patent_app_type] => utility [patent_app_number] => 16/395024 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 7016 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/395024
Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end Apr 24, 2019 Issued
Array ( [id] => 16048309 [patent_doc_number] => 10686040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end [patent_app_type] => utility [patent_app_number] => 16/395084 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 7016 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395084 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/395084
Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end Apr 24, 2019 Issued
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