
Hoai V. Pham
Examiner (ID: 18096)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2814, 2892, 2811 |
| Total Applications | 2250 |
| Issued Applications | 2043 |
| Pending Applications | 85 |
| Abandoned Applications | 160 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9086222
[patent_doc_number] => 08557649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-15
[patent_title] => 'Method for controlling structure height'
[patent_app_type] => utility
[patent_app_number] => 13/278301
[patent_app_country] => US
[patent_app_date] => 2011-10-21
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2869
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13278301
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/278301 | Method for controlling structure height | Oct 20, 2011 | Issued |
Array
(
[id] => 8780155
[patent_doc_number] => 20130102130
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-25
[patent_title] => 'BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION'
[patent_app_type] => utility
[patent_app_number] => 13/277956
[patent_app_country] => US
[patent_app_date] => 2011-10-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/277956 | Bulk fin-field effect transistors with well defined isolation | Oct 19, 2011 | Issued |
Array
(
[id] => 8159289
[patent_doc_number] => 20120100639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-26
[patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND MANUFACTURING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/278164
[patent_app_country] => US
[patent_app_date] => 2011-10-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/278164 | Semiconductor device manufacturing method and manufacturing apparatus | Oct 19, 2011 | Issued |
Array
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[patent_doc_number] => 08415232
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[patent_issue_date] => 2013-04-09
[patent_title] => 'Dividing method for wafer having die bonding film attached to the back side thereof'
[patent_app_type] => utility
[patent_app_number] => 13/277874
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[patent_app_date] => 2011-10-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/277874 | Dividing method for wafer having die bonding film attached to the back side thereof | Oct 19, 2011 | Issued |
Array
(
[id] => 7767205
[patent_doc_number] => 20120034736
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[patent_kind] => A1
[patent_issue_date] => 2012-02-09
[patent_title] => 'THIN-FILM TRANSISTORS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/277383 | Thin-film transistors | Oct 19, 2011 | Issued |
Array
(
[id] => 7750373
[patent_doc_number] => 20120025254
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[patent_issue_date] => 2012-02-02
[patent_title] => 'SEMICONDUCTOR LIGHT EMITTING DEVICE SUBSTRATE STRIPS AND PACKAGED SEMICONDUCTOR LIGHT EMITTING DEVICES'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/253657 | Semiconductor light emitting device substrate strips and packaged semiconductor light emitting devices | Oct 4, 2011 | Issued |
Array
(
[id] => 8571585
[patent_doc_number] => 08338230
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[patent_title] => 'System and method for multi-chip module die extraction and replacement'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/245909 | System and method for multi-chip module die extraction and replacement | Sep 26, 2011 | Issued |
Array
(
[id] => 9324133
[patent_doc_number] => 08659159
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[patent_kind] => B2
[patent_issue_date] => 2014-02-25
[patent_title] => 'Integrated circuit device with interconnects arranged parallel to each other and connected to contact via, and method for manufacturing same'
[patent_app_type] => utility
[patent_app_number] => 13/237825
[patent_app_country] => US
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Array
(
[id] => 8718025
[patent_doc_number] => 20130069242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-21
[patent_title] => 'ARRANGEMENT OF THROUGH-SUBSTRATE VIAS FOR STRESS RELIEF AND IMPROVED DENSITY'
[patent_app_type] => utility
[patent_app_number] => 13/237387
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/237387 | ARRANGEMENT OF THROUGH-SUBSTRATE VIAS FOR STRESS RELIEF AND IMPROVED DENSITY | Sep 19, 2011 | Abandoned |
Array
(
[id] => 8189025
[patent_doc_number] => 08183105
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-22
[patent_title] => 'Integrated circuit device with stress reduction layer'
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[patent_app_number] => 13/228884
[patent_app_country] => US
[patent_app_date] => 2011-09-09
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[firstpage_image] =>[orig_patent_app_number] => 13228884
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228884 | Integrated circuit device with stress reduction layer | Sep 8, 2011 | Issued |
Array
(
[id] => 7669627
[patent_doc_number] => 20110318896
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[patent_issue_date] => 2011-12-29
[patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/222286 | Method for manufacturing semiconductor device | Aug 30, 2011 | Issued |
Array
(
[id] => 7662900
[patent_doc_number] => 20110312169
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[patent_title] => 'ANTI-FUSE MEMORY CELL'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/219215 | Anti-fuse memory cell | Aug 25, 2011 | Issued |
Array
(
[id] => 7648762
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/213597 | Semiconductor memory device including multi-layer gate structure | Aug 18, 2011 | Issued |
Array
(
[id] => 8643224
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[patent_title] => 'Semiconductor package with under bump metallization routing'
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Array
(
[id] => 7558953
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Array
(
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/166273 | Nonvolatile memory device with multiple blocking layers and method of fabricating the same | Jun 21, 2011 | Issued |