Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9086222 [patent_doc_number] => 08557649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Method for controlling structure height' [patent_app_type] => utility [patent_app_number] => 13/278301 [patent_app_country] => US [patent_app_date] => 2011-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 2869 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13278301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/278301
Method for controlling structure height Oct 20, 2011 Issued
Array ( [id] => 8780155 [patent_doc_number] => 20130102130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION' [patent_app_type] => utility [patent_app_number] => 13/277956 [patent_app_country] => US [patent_app_date] => 2011-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13277956 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/277956
Bulk fin-field effect transistors with well defined isolation Oct 19, 2011 Issued
Array ( [id] => 8159289 [patent_doc_number] => 20120100639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND MANUFACTURING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/278164 [patent_app_country] => US [patent_app_date] => 2011-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7269 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20120100639.pdf [firstpage_image] =>[orig_patent_app_number] => 13278164 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/278164
Semiconductor device manufacturing method and manufacturing apparatus Oct 19, 2011 Issued
Array ( [id] => 8749400 [patent_doc_number] => 08415232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Dividing method for wafer having die bonding film attached to the back side thereof' [patent_app_type] => utility [patent_app_number] => 13/277874 [patent_app_country] => US [patent_app_date] => 2011-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3951 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13277874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/277874
Dividing method for wafer having die bonding film attached to the back side thereof Oct 19, 2011 Issued
Array ( [id] => 7767205 [patent_doc_number] => 20120034736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'THIN-FILM TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 13/277383 [patent_app_country] => US [patent_app_date] => 2011-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4197 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20120034736.pdf [firstpage_image] =>[orig_patent_app_number] => 13277383 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/277383
Thin-film transistors Oct 19, 2011 Issued
Array ( [id] => 7750373 [patent_doc_number] => 20120025254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'SEMICONDUCTOR LIGHT EMITTING DEVICE SUBSTRATE STRIPS AND PACKAGED SEMICONDUCTOR LIGHT EMITTING DEVICES' [patent_app_type] => utility [patent_app_number] => 13/253657 [patent_app_country] => US [patent_app_date] => 2011-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7563 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20120025254.pdf [firstpage_image] =>[orig_patent_app_number] => 13253657 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/253657
Semiconductor light emitting device substrate strips and packaged semiconductor light emitting devices Oct 4, 2011 Issued
Array ( [id] => 8571585 [patent_doc_number] => 08338230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'System and method for multi-chip module die extraction and replacement' [patent_app_type] => utility [patent_app_number] => 13/245909 [patent_app_country] => US [patent_app_date] => 2011-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3100 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13245909 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/245909
System and method for multi-chip module die extraction and replacement Sep 26, 2011 Issued
Array ( [id] => 9324133 [patent_doc_number] => 08659159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Integrated circuit device with interconnects arranged parallel to each other and connected to contact via, and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 13/237825 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 10628 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237825 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237825
Integrated circuit device with interconnects arranged parallel to each other and connected to contact via, and method for manufacturing same Sep 19, 2011 Issued
Array ( [id] => 8718025 [patent_doc_number] => 20130069242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'ARRANGEMENT OF THROUGH-SUBSTRATE VIAS FOR STRESS RELIEF AND IMPROVED DENSITY' [patent_app_type] => utility [patent_app_number] => 13/237387 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1748 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237387 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237387
ARRANGEMENT OF THROUGH-SUBSTRATE VIAS FOR STRESS RELIEF AND IMPROVED DENSITY Sep 19, 2011 Abandoned
Array ( [id] => 8189025 [patent_doc_number] => 08183105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Integrated circuit device with stress reduction layer' [patent_app_type] => utility [patent_app_number] => 13/228884 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183105.pdf [firstpage_image] =>[orig_patent_app_number] => 13228884 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228884
Integrated circuit device with stress reduction layer Sep 8, 2011 Issued
Array ( [id] => 7669627 [patent_doc_number] => 20110318896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/222286 [patent_app_country] => US [patent_app_date] => 2011-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17005 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13222286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/222286
Method for manufacturing semiconductor device Aug 30, 2011 Issued
Array ( [id] => 7662900 [patent_doc_number] => 20110312169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'ANTI-FUSE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/219215 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14248 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0312/20110312169.pdf [firstpage_image] =>[orig_patent_app_number] => 13219215 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219215
Anti-fuse memory cell Aug 25, 2011 Issued
Array ( [id] => 7648762 [patent_doc_number] => 20110298031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/213597 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12102 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20110298031.pdf [firstpage_image] =>[orig_patent_app_number] => 13213597 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/213597
Semiconductor memory device including multi-layer gate structure Aug 18, 2011 Issued
Array ( [id] => 8643224 [patent_doc_number] => 08368212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-05 [patent_title] => 'Semiconductor package with under bump metallization routing' [patent_app_type] => utility [patent_app_number] => 13/192303 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6844 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192303
Semiconductor package with under bump metallization routing Jul 26, 2011 Issued
Array ( [id] => 7558953 [patent_doc_number] => 20110272784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT CYLINDRICAL CAPACITOR AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/185873 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20110272784.pdf [firstpage_image] =>[orig_patent_app_number] => 13185873 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185873
Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same Jul 18, 2011 Issued
Array ( [id] => 7561351 [patent_doc_number] => 20110275184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/184116 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6794 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20110275184.pdf [firstpage_image] =>[orig_patent_app_number] => 13184116 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/184116
Semiconductor device Jul 14, 2011 Issued
Array ( [id] => 8165752 [patent_doc_number] => 08174080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/184159 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6836 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174080.pdf [firstpage_image] =>[orig_patent_app_number] => 13184159 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/184159
Semiconductor device Jul 14, 2011 Issued
Array ( [id] => 8190254 [patent_doc_number] => 08183679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Electronic part package' [patent_app_type] => utility [patent_app_number] => 13/182923 [patent_app_country] => US [patent_app_date] => 2011-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 31 [patent_no_of_words] => 4512 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183679.pdf [firstpage_image] =>[orig_patent_app_number] => 13182923 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/182923
Electronic part package Jul 13, 2011 Issued
Array ( [id] => 7479805 [patent_doc_number] => 20110248262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'DISPLAY DEVICE HAVING OXIDE THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/166478 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5833 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248262.pdf [firstpage_image] =>[orig_patent_app_number] => 13166478 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166478
Display device having oxide thin film transistor and fabrication method thereof Jun 21, 2011 Issued
Array ( [id] => 7486183 [patent_doc_number] => 20110250746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/166273 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11742 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20110250746.pdf [firstpage_image] =>[orig_patent_app_number] => 13166273 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166273
Nonvolatile memory device with multiple blocking layers and method of fabricating the same Jun 21, 2011 Issued
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