Hoai V. Pham

Array ( [id] => 18698488 [patent_doc_number] => 20230328968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/116537 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18116537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18473374 [patent_doc_number] => 20230207662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/174902 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19124842 [patent_doc_number] => 11968850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Light-emitting element having an organic compound and a transition metal [patent_app_type] => utility [patent_app_number] => 18/110999 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 136 [patent_no_of_words] => 60888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20307071 [patent_doc_number] => 12453082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Semiconductor device having a cell separation pattern in contact with the bit line contact [patent_app_type] => utility [patent_app_number] => 18/109442 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 4207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20612568 [patent_doc_number] => 12588184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Transistor, semiconductor structure, memory, and method for forming same [patent_app_type] => utility [patent_app_number] => 18/168542 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 42 [patent_no_of_words] => 9558 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20361704 [patent_doc_number] => 12477722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Semiconductor memory device comprises a bit line having a plurality of pins extending toward a substrate [patent_app_type] => utility [patent_app_number] => 18/108669 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18108669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19495748 [patent_doc_number] => 12114487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Semiconductor memory device having bit lines and isolation fins disposed on the substrate [patent_app_type] => utility [patent_app_number] => 18/108666 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4678 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18108666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18914514 [patent_doc_number] => 11877520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Magnetoresistive random access memory having a ring of magnetic tunneling junction region surrounding an array region [patent_app_type] => utility [patent_app_number] => 18/108003 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3231 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18108003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18442280 [patent_doc_number] => 20230189576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 18/107853 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19366061 [patent_doc_number] => 20240268095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => 4F2 DRAM Including Buried Bitline [patent_app_type] => utility [patent_app_number] => 18/164082 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18426071 [patent_doc_number] => 20230180536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/161836 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18731398 [patent_doc_number] => 20230345706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SAME, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/157073 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18951066 [patent_doc_number] => 11894372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Stacked trigate transistors with dielectric isolation and process for forming such [patent_app_type] => utility [patent_app_number] => 18/095973 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20260538 [patent_doc_number] => 12432909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Semiconductor memory device having an ohmic contact on the impurity regions [patent_app_type] => utility [patent_app_number] => 18/093561 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 4592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20307074 [patent_doc_number] => 12453085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Semiconductor memory device having connection pattern between the bit line contact and the separation insulating pattern [patent_app_type] => utility [patent_app_number] => 18/093568 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 4800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18731387 [patent_doc_number] => 20230345695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/149178 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19178112 [patent_doc_number] => 20240164086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR DEVICE, MEMORY AND STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/090108 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19733934 [patent_doc_number] => 12211936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Strained-channel fin FETs [patent_app_type] => utility [patent_app_number] => 18/146962 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 5310 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20191195 [patent_doc_number] => 12402333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Electronic component comprising a 3D capacitive structure [patent_app_type] => utility [patent_app_number] => 18/087579 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 1169 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18087579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20376759 [patent_doc_number] => 12484215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Memory cell with improved insulating structure [patent_app_type] => utility [patent_app_number] => 18/083921 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5619 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083921 [rel_patent_id] =>[rel_patent_doc_number] =>)