Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19366061 [patent_doc_number] => 20240268095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => 4F2 DRAM Including Buried Bitline [patent_app_type] => utility [patent_app_number] => 18/164082 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164082 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164082
4F2 DRAM Including Buried Bitline Feb 2, 2023 Pending
Array ( [id] => 18426071 [patent_doc_number] => 20230180536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/161836 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161836 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/161836
Lift-off process for manufacturing an organic light-emitting display apparatus Jan 29, 2023 Issued
Array ( [id] => 18731398 [patent_doc_number] => 20230345706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SAME, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/157073 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157073
Semiconductor structure, method for manufacturing same, and memory Jan 19, 2023 Issued
Array ( [id] => 18731398 [patent_doc_number] => 20230345706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SAME, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/157073 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157073
Semiconductor structure, method for manufacturing same, and memory Jan 19, 2023 Issued
Array ( [id] => 18951066 [patent_doc_number] => 11894372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Stacked trigate transistors with dielectric isolation and process for forming such [patent_app_type] => utility [patent_app_number] => 18/095973 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095973 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/095973
Stacked trigate transistors with dielectric isolation and process for forming such Jan 10, 2023 Issued
Array ( [id] => 20307074 [patent_doc_number] => 12453085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Semiconductor memory device having connection pattern between the bit line contact and the separation insulating pattern [patent_app_type] => utility [patent_app_number] => 18/093568 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 4800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093568 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093568
Semiconductor memory device having connection pattern between the bit line contact and the separation insulating pattern Jan 4, 2023 Issued
Array ( [id] => 20260538 [patent_doc_number] => 12432909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Semiconductor memory device having an ohmic contact on the impurity regions [patent_app_type] => utility [patent_app_number] => 18/093561 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 4592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093561 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093561
Semiconductor memory device having an ohmic contact on the impurity regions Jan 4, 2023 Issued
Array ( [id] => 18731387 [patent_doc_number] => 20230345695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/149178 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149178
Method of forming bit line contact structure using series of pickling processes to remove native oxide on surface of the active areas Jan 2, 2023 Issued
Array ( [id] => 19178112 [patent_doc_number] => 20240164086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR DEVICE, MEMORY AND STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/090108 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090108 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090108
Semiconductor device, memory and storage system Dec 27, 2022 Issued
Array ( [id] => 19178112 [patent_doc_number] => 20240164086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR DEVICE, MEMORY AND STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/090108 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090108 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090108
Semiconductor device, memory and storage system Dec 27, 2022 Issued
Array ( [id] => 19733934 [patent_doc_number] => 12211936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Strained-channel fin FETs [patent_app_type] => utility [patent_app_number] => 18/146962 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 5310 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146962 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146962
Strained-channel fin FETs Dec 26, 2022 Issued
Array ( [id] => 20191195 [patent_doc_number] => 12402333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Electronic component comprising a 3D capacitive structure [patent_app_type] => utility [patent_app_number] => 18/087579 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 1169 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18087579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/087579
Electronic component comprising a 3D capacitive structure Dec 21, 2022 Issued
Array ( [id] => 20191195 [patent_doc_number] => 12402333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Electronic component comprising a 3D capacitive structure [patent_app_type] => utility [patent_app_number] => 18/087579 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 1169 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18087579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/087579
Electronic component comprising a 3D capacitive structure Dec 21, 2022 Issued
Array ( [id] => 20376759 [patent_doc_number] => 12484215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Memory cell with improved insulating structure [patent_app_type] => utility [patent_app_number] => 18/083921 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5619 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083921 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/083921
Memory cell with improved insulating structure Dec 18, 2022 Issued
Array ( [id] => 18323504 [patent_doc_number] => 20230121632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => LIGHT-EMITTING DEVICE INCLUDING A LIGHT-TRANSMITTING INTERCONNECT LOCATED OVER A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/083118 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083118 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/083118
Light-emitting device including a light-transmitting interconnect located over a substrate Dec 15, 2022 Issued
Array ( [id] => 18308156 [patent_doc_number] => 20230112056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 18/080740 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080740 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/080740
Semiconductor packages having thermal conductive pattern Dec 13, 2022 Issued
Array ( [id] => 18983510 [patent_doc_number] => 11908697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Interconnect structure having a carbon-containing barrier layer [patent_app_type] => utility [patent_app_number] => 18/064341 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064341
Interconnect structure having a carbon-containing barrier layer Dec 11, 2022 Issued
Array ( [id] => 20276422 [patent_doc_number] => 12446211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Memory device having ultra-lightly doped region [patent_app_type] => utility [patent_app_number] => 18/078349 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 5019 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078349
Memory device having ultra-lightly doped region Dec 8, 2022 Issued
Array ( [id] => 20389321 [patent_doc_number] => 12489056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Semiconductor device having an upper end of a lower spacer structure on a level same as or lower than a lower end of a storage node contact [patent_app_type] => utility [patent_app_number] => 18/062811 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 3561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062811 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062811
Semiconductor device having an upper end of a lower spacer structure on a level same as or lower than a lower end of a storage node contact Dec 6, 2022 Issued
Array ( [id] => 20389321 [patent_doc_number] => 12489056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Semiconductor device having an upper end of a lower spacer structure on a level same as or lower than a lower end of a storage node contact [patent_app_type] => utility [patent_app_number] => 18/062811 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 3561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062811 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062811
Semiconductor device having an upper end of a lower spacer structure on a level same as or lower than a lower end of a storage node contact Dec 6, 2022 Issued
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