Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6374931 [patent_doc_number] => 20100301305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'PHASE CHANGE MEMORY DEVICE WITH ALTERNATING ADJACENT CONDUCTION CONTACTS AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/641535 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301305.pdf [firstpage_image] =>[orig_patent_app_number] => 12641535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/641535
Phase change memory device with alternating adjacent conduction contacts and fabrication method thereof Dec 17, 2009 Issued
Array ( [id] => 7530323 [patent_doc_number] => 07842545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Semiconductor package having insulated metal substrate and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/641554 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3557 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/842/07842545.pdf [firstpage_image] =>[orig_patent_app_number] => 12641554 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/641554
Semiconductor package having insulated metal substrate and method of fabricating the same Dec 17, 2009 Issued
Array ( [id] => 8005845 [patent_doc_number] => 08084323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Stack capacitor of memory device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 12/640846 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 2284 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/084/08084323.pdf [firstpage_image] =>[orig_patent_app_number] => 12640846 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640846
Stack capacitor of memory device and fabrication method thereof Dec 16, 2009 Issued
Array ( [id] => 6392432 [patent_doc_number] => 20100163894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'Group III nitride-based compound semiconductor light-emitting device' [patent_app_type] => utility [patent_app_number] => 12/654350 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12622 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20100163894.pdf [firstpage_image] =>[orig_patent_app_number] => 12654350 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/654350
Group III nitride-based compound semiconductor light-emitting device Dec 16, 2009 Issued
Array ( [id] => 8213972 [patent_doc_number] => 08193022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Back side illuminaton image sensor and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/641010 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4624 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193022.pdf [firstpage_image] =>[orig_patent_app_number] => 12641010 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/641010
Back side illuminaton image sensor and method for manufacturing the same Dec 16, 2009 Issued
Array ( [id] => 8176919 [patent_doc_number] => 08178381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Back side illumination image sensor and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/640954 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4609 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/178/08178381.pdf [firstpage_image] =>[orig_patent_app_number] => 12640954 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640954
Back side illumination image sensor and method for manufacturing the same Dec 16, 2009 Issued
Array ( [id] => 6392820 [patent_doc_number] => 20100163972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'MULTI-DRAIN SEMICONDUCTOR POWER DEVICE AND EDGE-TERMINATION STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/640980 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4675 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20100163972.pdf [firstpage_image] =>[orig_patent_app_number] => 12640980 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640980
Multi-drain semiconductor power device and edge-termination structure thereof Dec 16, 2009 Issued
Array ( [id] => 6604586 [patent_doc_number] => 20100171130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'Semiconductor device and fabrication method' [patent_app_type] => utility [patent_app_number] => 12/654386 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7495 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20100171130.pdf [firstpage_image] =>[orig_patent_app_number] => 12654386 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/654386
Semiconductor device and fabrication method Dec 16, 2009 Issued
Array ( [id] => 7762008 [patent_doc_number] => 08114694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Method for manufacturing back side illuminaton image sensor' [patent_app_type] => utility [patent_app_number] => 12/640874 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4369 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/114/08114694.pdf [firstpage_image] =>[orig_patent_app_number] => 12640874 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640874
Method for manufacturing back side illuminaton image sensor Dec 16, 2009 Issued
Array ( [id] => 6392288 [patent_doc_number] => 20100163870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'Structure and Method for Testing MEMS Devices' [patent_app_type] => utility [patent_app_number] => 12/641022 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20100163870.pdf [firstpage_image] =>[orig_patent_app_number] => 12641022 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/641022
Structure and method for testing MEMS devices Dec 16, 2009 Issued
Array ( [id] => 22164 [patent_doc_number] => 07799623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Method for manufacturing semiconductor device having LDMOS transistor' [patent_app_type] => utility [patent_app_number] => 12/654230 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6101 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/799/07799623.pdf [firstpage_image] =>[orig_patent_app_number] => 12654230 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/654230
Method for manufacturing semiconductor device having LDMOS transistor Dec 14, 2009 Issued
Array ( [id] => 6215868 [patent_doc_number] => 20100052001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'LED PACKAGING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/615963 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20100052001.pdf [firstpage_image] =>[orig_patent_app_number] => 12615963 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/615963
LED packaging structure Nov 9, 2009 Issued
Array ( [id] => 6587028 [patent_doc_number] => 20100047971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages' [patent_app_type] => utility [patent_app_number] => 12/589409 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5578 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20100047971.pdf [firstpage_image] =>[orig_patent_app_number] => 12589409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/589409
Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages Oct 21, 2009 Issued
Array ( [id] => 6587028 [patent_doc_number] => 20100047971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages' [patent_app_type] => utility [patent_app_number] => 12/589409 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5578 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20100047971.pdf [firstpage_image] =>[orig_patent_app_number] => 12589409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/589409
Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages Oct 21, 2009 Issued
Array ( [id] => 6447779 [patent_doc_number] => 20100038738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'Capacitive Bypass' [patent_app_type] => utility [patent_app_number] => 12/582095 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2515 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20100038738.pdf [firstpage_image] =>[orig_patent_app_number] => 12582095 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582095
Capacitive bypass Oct 19, 2009 Issued
Array ( [id] => 6036532 [patent_doc_number] => 20110089581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'SEMICONDUCTOR WAFER HAVING SCRIBE LANE ALIGNMENT MARKS FOR REDUCING CRACK PROPAGATION' [patent_app_type] => utility [patent_app_number] => 12/581549 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20110089581.pdf [firstpage_image] =>[orig_patent_app_number] => 12581549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581549
Semiconductor wafer having scribe lane alignment marks for reducing crack propagation Oct 18, 2009 Issued
Array ( [id] => 6458292 [patent_doc_number] => 20100090326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Stack package' [patent_app_type] => utility [patent_app_number] => 12/588382 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7035 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20100090326.pdf [firstpage_image] =>[orig_patent_app_number] => 12588382 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588382
Stack package Oct 13, 2009 Issued
Array ( [id] => 8104963 [patent_doc_number] => 08154128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => '3D integrated circuit layer interconnect' [patent_app_type] => utility [patent_app_number] => 12/579192 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 9739 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/154/08154128.pdf [firstpage_image] =>[orig_patent_app_number] => 12579192 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/579192
3D integrated circuit layer interconnect Oct 13, 2009 Issued
Array ( [id] => 8202678 [patent_doc_number] => 08188459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Devices based on SI/nitride structures' [patent_app_type] => utility [patent_app_number] => 12/577892 [patent_app_country] => US [patent_app_date] => 2009-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 4677 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/188/08188459.pdf [firstpage_image] =>[orig_patent_app_number] => 12577892 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577892
Devices based on SI/nitride structures Oct 12, 2009 Issued
Array ( [id] => 4539461 [patent_doc_number] => 07875551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Methods of forming integrated circuit devices using contact hole spacers to improve contact isolation' [patent_app_type] => utility [patent_app_number] => 12/575682 [patent_app_country] => US [patent_app_date] => 2009-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 3133 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/875/07875551.pdf [firstpage_image] =>[orig_patent_app_number] => 12575682 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575682
Methods of forming integrated circuit devices using contact hole spacers to improve contact isolation Oct 7, 2009 Issued
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