
Hoai V. Pham
Examiner (ID: 18096)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2814, 2892, 2811 |
| Total Applications | 2250 |
| Issued Applications | 2043 |
| Pending Applications | 85 |
| Abandoned Applications | 160 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5461651
[patent_doc_number] => 20090321851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-31
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/480062
[patent_app_country] => US
[patent_app_date] => 2009-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 10022
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0321/20090321851.pdf
[firstpage_image] =>[orig_patent_app_number] => 12480062
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/480062 | Semiconductor device including a halo layer and method of fabricating the same | Jun 7, 2009 | Issued |
Array
(
[id] => 9552847
[patent_doc_number] => 08759898
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Memory with a read-only EEPROM-type structure'
[patent_app_type] => utility
[patent_app_number] => 12/990682
[patent_app_country] => US
[patent_app_date] => 2009-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 28
[patent_no_of_words] => 5385
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12990682
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/990682 | Memory with a read-only EEPROM-type structure | May 11, 2009 | Issued |
Array
(
[id] => 7492327
[patent_doc_number] => 08030719
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-04
[patent_title] => 'Thermal sensing and reset protection for an integrated circuit chip'
[patent_app_type] => utility
[patent_app_number] => 12/387892
[patent_app_country] => US
[patent_app_date] => 2009-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2193
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/030/08030719.pdf
[firstpage_image] =>[orig_patent_app_number] => 12387892
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/387892 | Thermal sensing and reset protection for an integrated circuit chip | May 7, 2009 | Issued |
Array
(
[id] => 8386578
[patent_doc_number] => 08263978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-11
[patent_title] => 'Thin film transistor and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/453295
[patent_app_country] => US
[patent_app_date] => 2009-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3352
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12453295
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/453295 | Thin film transistor and method of manufacturing the same | May 5, 2009 | Issued |
Array
(
[id] => 5313641
[patent_doc_number] => 20090278239
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-12
[patent_title] => 'Silicon Wafer and Production Method Thereof'
[patent_app_type] => utility
[patent_app_number] => 12/436692
[patent_app_country] => US
[patent_app_date] => 2009-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2451
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0278/20090278239.pdf
[firstpage_image] =>[orig_patent_app_number] => 12436692
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/436692 | Thin silicon wafer with high gettering ability and production method thereof | May 5, 2009 | Issued |
Array
(
[id] => 6417335
[patent_doc_number] => 20100276794
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-04
[patent_title] => 'SYSTEM AND METHOD FOR MULTI-CHIP MODULE DIE EXTRACTION AND REPLACEMENT'
[patent_app_type] => utility
[patent_app_number] => 12/432672
[patent_app_country] => US
[patent_app_date] => 2009-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3068
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0276/20100276794.pdf
[firstpage_image] =>[orig_patent_app_number] => 12432672
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/432672 | System and method for multi-chip module die extraction and replacement | Apr 28, 2009 | Issued |
Array
(
[id] => 6311945
[patent_doc_number] => 20100111310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-06
[patent_title] => 'AUDIO SIGNAL PROCESSING APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/430988
[patent_app_country] => US
[patent_app_date] => 2009-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8793
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0111/20100111310.pdf
[firstpage_image] =>[orig_patent_app_number] => 12430988
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/430988 | Audio signal processing apparatus | Apr 27, 2009 | Issued |
Array
(
[id] => 5483253
[patent_doc_number] => 20090273018
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-05
[patent_title] => 'NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/430481
[patent_app_country] => US
[patent_app_date] => 2009-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11742
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20090273018.pdf
[firstpage_image] =>[orig_patent_app_number] => 12430481
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/430481 | Nonvolatile memory device with multiple blocking layers and method of fabricating the same | Apr 26, 2009 | Issued |
Array
(
[id] => 4431770
[patent_doc_number] => 07968355
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-06-28
[patent_title] => 'Luminous devices, packages and systems containing the same, and fabricating methods thereof'
[patent_app_type] => utility
[patent_app_number] => 12/386882
[patent_app_country] => US
[patent_app_date] => 2009-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 50
[patent_no_of_words] => 19492
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/968/07968355.pdf
[firstpage_image] =>[orig_patent_app_number] => 12386882
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/386882 | Luminous devices, packages and systems containing the same, and fabricating methods thereof | Apr 23, 2009 | Issued |
Array
(
[id] => 4538225
[patent_doc_number] => 07888777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-15
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/428991
[patent_app_country] => US
[patent_app_date] => 2009-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5756
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/888/07888777.pdf
[firstpage_image] =>[orig_patent_app_number] => 12428991
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/428991 | Semiconductor device and method for manufacturing the same | Apr 22, 2009 | Issued |
Array
(
[id] => 5555633
[patent_doc_number] => 20090267210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-29
[patent_title] => 'INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/428762
[patent_app_country] => US
[patent_app_date] => 2009-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3294
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20090267210.pdf
[firstpage_image] =>[orig_patent_app_number] => 12428762
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/428762 | INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF | Apr 22, 2009 | Abandoned |
Array
(
[id] => 5395062
[patent_doc_number] => 20090315125
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-24
[patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS WITH BILAYER DIELECTRICS'
[patent_app_type] => utility
[patent_app_number] => 12/426477
[patent_app_country] => US
[patent_app_date] => 2009-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2469
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0315/20090315125.pdf
[firstpage_image] =>[orig_patent_app_number] => 12426477
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/426477 | Semiconductor devices and methods with bilayer dielectrics | Apr 19, 2009 | Issued |
Array
(
[id] => 4435346
[patent_doc_number] => 07898059
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-01
[patent_title] => 'Semiconductor device comprising passive components'
[patent_app_type] => utility
[patent_app_number] => 12/426837
[patent_app_country] => US
[patent_app_date] => 2009-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 9831
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/898/07898059.pdf
[firstpage_image] =>[orig_patent_app_number] => 12426837
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/426837 | Semiconductor device comprising passive components | Apr 19, 2009 | Issued |
Array
(
[id] => 4577027
[patent_doc_number] => 07829995
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-09
[patent_title] => 'Semiconductor device and method of fabrication'
[patent_app_type] => utility
[patent_app_number] => 12/425682
[patent_app_country] => US
[patent_app_date] => 2009-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 29
[patent_no_of_words] => 7061
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/829/07829995.pdf
[firstpage_image] =>[orig_patent_app_number] => 12425682
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/425682 | Semiconductor device and method of fabrication | Apr 16, 2009 | Issued |
Array
(
[id] => 54968
[patent_doc_number] => 07768067
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-03
[patent_title] => 'DMOS transistor'
[patent_app_type] => utility
[patent_app_number] => 12/425592
[patent_app_country] => US
[patent_app_date] => 2009-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2489
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/768/07768067.pdf
[firstpage_image] =>[orig_patent_app_number] => 12425592
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/425592 | DMOS transistor | Apr 16, 2009 | Issued |
Array
(
[id] => 5527297
[patent_doc_number] => 20090197374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-06
[patent_title] => 'METHOD OF FABRICATING CHIP PACKAGE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/423811
[patent_app_country] => US
[patent_app_date] => 2009-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4119
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20090197374.pdf
[firstpage_image] =>[orig_patent_app_number] => 12423811
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/423811 | Method of fabricating chip package structure | Apr 14, 2009 | Issued |
Array
(
[id] => 5480230
[patent_doc_number] => 20090203187
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-13
[patent_title] => 'Method of Manufacturing SOI Substrate'
[patent_app_type] => utility
[patent_app_number] => 12/423585
[patent_app_country] => US
[patent_app_date] => 2009-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 18055
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0203/20090203187.pdf
[firstpage_image] =>[orig_patent_app_number] => 12423585
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/423585 | Method of manufacturing SOI substrate | Apr 13, 2009 | Issued |
Array
(
[id] => 7504700
[patent_doc_number] => 08035166
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-11
[patent_title] => 'Integrated circuit device with stress reduction layer'
[patent_app_type] => utility
[patent_app_number] => 12/420672
[patent_app_country] => US
[patent_app_date] => 2009-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8439
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/035/08035166.pdf
[firstpage_image] =>[orig_patent_app_number] => 12420672
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/420672 | Integrated circuit device with stress reduction layer | Apr 7, 2009 | Issued |
Array
(
[id] => 93110
[patent_doc_number] => 07737543
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-15
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/415782
[patent_app_country] => US
[patent_app_date] => 2009-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 84
[patent_figures_cnt] => 84
[patent_no_of_words] => 21225
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/737/07737543.pdf
[firstpage_image] =>[orig_patent_app_number] => 12415782
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/415782 | Semiconductor device and method of manufacturing the same | Mar 30, 2009 | Issued |
Array
(
[id] => 5458306
[patent_doc_number] => 20090258458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-15
[patent_title] => 'DFN semiconductor package having reduced electrical resistance'
[patent_app_type] => utility
[patent_app_number] => 12/384100
[patent_app_country] => US
[patent_app_date] => 2009-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3500
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0258/20090258458.pdf
[firstpage_image] =>[orig_patent_app_number] => 12384100
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/384100 | DFN semiconductor package having reduced electrical resistance | Mar 29, 2009 | Issued |