Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4573399 [patent_doc_number] => 07824951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Method of fabricating an integrated circuit having a memory including a low-k dielectric material' [patent_app_type] => utility [patent_app_number] => 12/050727 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2924 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/824/07824951.pdf [firstpage_image] =>[orig_patent_app_number] => 12050727 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/050727
Method of fabricating an integrated circuit having a memory including a low-k dielectric material Mar 17, 2008 Issued
Array ( [id] => 4927487 [patent_doc_number] => 20080166850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'LOCAL COLLECTOR IMPLANT STRUCTURE FOR HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODOF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/047457 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3062 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20080166850.pdf [firstpage_image] =>[orig_patent_app_number] => 12047457 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047457
Local collector implant structure for heterojunction bipolar transistors and method of forming the same Mar 12, 2008 Issued
Array ( [id] => 4715075 [patent_doc_number] => 20080237597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/043615 [patent_app_country] => US [patent_app_date] => 2008-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 6455 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237597.pdf [firstpage_image] =>[orig_patent_app_number] => 12043615 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/043615
Thin film transistor array panel and manufacturing method thereof Mar 5, 2008 Issued
Array ( [id] => 6215731 [patent_doc_number] => 20100051921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'ORGANIC FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/532382 [patent_app_country] => US [patent_app_date] => 2008-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6017 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20100051921.pdf [firstpage_image] =>[orig_patent_app_number] => 12532382 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/532382
Organic field effect transistor Mar 5, 2008 Issued
Array ( [id] => 307806 [patent_doc_number] => 07531880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/040072 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 6541 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531880.pdf [firstpage_image] =>[orig_patent_app_number] => 12040072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/040072
Semiconductor device and manufacturing method thereof Feb 28, 2008 Issued
Array ( [id] => 4873267 [patent_doc_number] => 20080200001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'METHOD OF PRODUCING A TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/030672 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5358 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20080200001.pdf [firstpage_image] =>[orig_patent_app_number] => 12030672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030672
Method of producing a transistor Feb 12, 2008 Issued
Array ( [id] => 5477718 [patent_doc_number] => 20090200675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Passivated Copper Chip Pads' [patent_app_type] => utility [patent_app_number] => 12/029127 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3039 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20090200675.pdf [firstpage_image] =>[orig_patent_app_number] => 12029127 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/029127
Passivated Copper Chip Pads Feb 10, 2008 Abandoned
Array ( [id] => 4864800 [patent_doc_number] => 20080143859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'METHODS FOR MAKING A PIXEL CELL WITH A TRANSPARENT CONDUCTIVE INTERCONNECT LINE FOR FOCUSING LIGHT' [patent_app_type] => utility [patent_app_number] => 12/026210 [patent_app_country] => US [patent_app_date] => 2008-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5067 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20080143859.pdf [firstpage_image] =>[orig_patent_app_number] => 12026210 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/026210
Methods for making a pixel cell with a transparent conductive interconnect line for focusing light Feb 4, 2008 Issued
Array ( [id] => 4472304 [patent_doc_number] => 07943995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/068161 [patent_app_country] => US [patent_app_date] => 2008-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 7197 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/943/07943995.pdf [firstpage_image] =>[orig_patent_app_number] => 12068161 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/068161
NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same Feb 3, 2008 Issued
Array ( [id] => 5518553 [patent_doc_number] => 20090026534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Trench MOSFET and method of making the same' [patent_app_type] => utility [patent_app_number] => 12/010972 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3079 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20090026534.pdf [firstpage_image] =>[orig_patent_app_number] => 12010972 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010972
Trench MOSFET and method of making the same Jan 30, 2008 Abandoned
Array ( [id] => 132724 [patent_doc_number] => 07701004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Semiconductor device and method of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 12/010935 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 3857 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701004.pdf [firstpage_image] =>[orig_patent_app_number] => 12010935 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010935
Semiconductor device and method of manufacturing thereof Jan 30, 2008 Issued
Array ( [id] => 583332 [patent_doc_number] => 07445988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Trench memory' [patent_app_type] => utility [patent_app_number] => 12/023175 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2900 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/445/07445988.pdf [firstpage_image] =>[orig_patent_app_number] => 12023175 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023175
Trench memory Jan 30, 2008 Issued
Array ( [id] => 5377384 [patent_doc_number] => 20090189223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'Complementary Metal Gate Dense Interconnect and Method of Manufacturing' [patent_app_type] => utility [patent_app_number] => 12/022292 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20090189223.pdf [firstpage_image] =>[orig_patent_app_number] => 12022292 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/022292
Complementary metal gate dense interconnect and method of manufacturing Jan 29, 2008 Issued
Array ( [id] => 143016 [patent_doc_number] => 07692194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/015362 [patent_app_country] => US [patent_app_date] => 2008-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 102 [patent_no_of_words] => 37175 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/692/07692194.pdf [firstpage_image] =>[orig_patent_app_number] => 12015362 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/015362
Semiconductor device Jan 15, 2008 Issued
Array ( [id] => 4904094 [patent_doc_number] => 20080113507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/014127 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2877 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20080113507.pdf [firstpage_image] =>[orig_patent_app_number] => 12014127 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/014127
Poly filled substrate contact on SOI structure Jan 14, 2008 Issued
Array ( [id] => 4863812 [patent_doc_number] => 20080142871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/007420 [patent_app_country] => US [patent_app_date] => 2008-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7765 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20080142871.pdf [firstpage_image] =>[orig_patent_app_number] => 12007420 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/007420
Semiconductor device having side wall spacers Jan 9, 2008 Issued
Array ( [id] => 4965383 [patent_doc_number] => 20080108203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Multi-Layer Electrode and Method of Forming the Same' [patent_app_type] => utility [patent_app_number] => 11/972147 [patent_app_country] => US [patent_app_date] => 2008-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3320 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20080108203.pdf [firstpage_image] =>[orig_patent_app_number] => 11972147 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972147
Multi-Layer Electrode and Method of Forming the Same Jan 9, 2008 Abandoned
Array ( [id] => 4745805 [patent_doc_number] => 20080090407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME' [patent_app_type] => utility [patent_app_number] => 11/953927 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3874 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20080090407.pdf [firstpage_image] =>[orig_patent_app_number] => 11953927 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953927
Terminal pad structures and methods of fabricating same Dec 10, 2007 Issued
Array ( [id] => 4893494 [patent_doc_number] => 20080102592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Method for manufacturing bipolar transistor' [patent_app_type] => utility [patent_app_number] => 12/001226 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3673 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20080102592.pdf [firstpage_image] =>[orig_patent_app_number] => 12001226 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/001226
Method for manufacturing bipolar transistor Dec 9, 2007 Issued
Array ( [id] => 4745728 [patent_doc_number] => 20080090330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF CIRCUIT ELEMENT CHIPS AND A MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/947335 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5501 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20080090330.pdf [firstpage_image] =>[orig_patent_app_number] => 11947335 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947335
Semiconductor device including a plurality of circuit element chips and a manufacturing method thereof Nov 28, 2007 Issued
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