Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5120063 [patent_doc_number] => 20070141777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Method of forming a contact using a sacrificial structure' [patent_app_type] => utility [patent_app_number] => 11/706690 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7027 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20070141777.pdf [firstpage_image] =>[orig_patent_app_number] => 11706690 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706690
Method of forming a contact using a sacrificial structure Feb 14, 2007 Issued
Array ( [id] => 908252 [patent_doc_number] => 07332793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/705748 [patent_app_country] => US [patent_app_date] => 2007-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5578 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332793.pdf [firstpage_image] =>[orig_patent_app_number] => 11705748 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/705748
Semiconductor device Feb 13, 2007 Issued
Array ( [id] => 408145 [patent_doc_number] => 07285462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/650126 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 8896 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285462.pdf [firstpage_image] =>[orig_patent_app_number] => 11650126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/650126
Semiconductor memory device with trench-type stacked cell capacitors and method for manufacturing the same Jan 4, 2007 Issued
Array ( [id] => 853302 [patent_doc_number] => 07378688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-27 [patent_title] => 'Method and apparatus for a low noise JFET device on a standard CMOS process' [patent_app_type] => utility [patent_app_number] => 11/618598 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5144 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/378/07378688.pdf [firstpage_image] =>[orig_patent_app_number] => 11618598 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618598
Method and apparatus for a low noise JFET device on a standard CMOS process Dec 28, 2006 Issued
Array ( [id] => 4985944 [patent_doc_number] => 20070152282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Semiconductor Device and Fabrication Method Thereof' [patent_app_type] => utility [patent_app_number] => 11/615078 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20070152282.pdf [firstpage_image] =>[orig_patent_app_number] => 11615078 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615078
Semiconductor Device and Fabrication Method Thereof Dec 21, 2006 Abandoned
Array ( [id] => 5022925 [patent_doc_number] => 20070148891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method for manufacturing bipolar transistor' [patent_app_type] => utility [patent_app_number] => 11/644648 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3652 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148891.pdf [firstpage_image] =>[orig_patent_app_number] => 11644648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644648
Method for manufacturing bipolar transistor Dec 21, 2006 Issued
Array ( [id] => 404957 [patent_doc_number] => 07288790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Thin film transistor array panel and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/612055 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 6459 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288790.pdf [firstpage_image] =>[orig_patent_app_number] => 11612055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612055
Thin film transistor array panel and manufacturing method thereof Dec 17, 2006 Issued
Array ( [id] => 925647 [patent_doc_number] => 07316945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-08 [patent_title] => 'Method of fabricating a fin field effect transistor in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/608589 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1649 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/316/07316945.pdf [firstpage_image] =>[orig_patent_app_number] => 11608589 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608589
Method of fabricating a fin field effect transistor in a semiconductor device Dec 7, 2006 Issued
Array ( [id] => 377392 [patent_doc_number] => 07312493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/607328 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2003 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312493.pdf [firstpage_image] =>[orig_patent_app_number] => 11607328 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607328
Semiconductor device and method of manufacturing the same Nov 29, 2006 Issued
Array ( [id] => 5168840 [patent_doc_number] => 20070069271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Methods for manufacturing capacitors for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/605272 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4658 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069271.pdf [firstpage_image] =>[orig_patent_app_number] => 11605272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605272
Methods for manufacturing capacitors for semiconductor devices Nov 28, 2006 Abandoned
Array ( [id] => 5168946 [patent_doc_number] => 20070069377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'CLOCK DISTRIBUTION NETWORKS AND CONDUCTIVE LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/559805 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5095 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069377.pdf [firstpage_image] =>[orig_patent_app_number] => 11559805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559805
CLOCK DISTRIBUTION NETWORKS AND CONDUCTIVE LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS Nov 13, 2006 Abandoned
Array ( [id] => 299790 [patent_doc_number] => 07537989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Method for manufacturing SOI substrate' [patent_app_type] => utility [patent_app_number] => 11/559347 [patent_app_country] => US [patent_app_date] => 2006-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 18055 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/537/07537989.pdf [firstpage_image] =>[orig_patent_app_number] => 11559347 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559347
Method for manufacturing SOI substrate Nov 12, 2006 Issued
Array ( [id] => 4968533 [patent_doc_number] => 20070108535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/591549 [patent_app_country] => US [patent_app_date] => 2006-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5238 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20070108535.pdf [firstpage_image] =>[orig_patent_app_number] => 11591549 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/591549
Field effect transistor having contact plugs in the source region greater than in the drain region Nov 1, 2006 Issued
Array ( [id] => 4610470 [patent_doc_number] => 07994619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Bridge stack integrated circuit package system' [patent_app_type] => utility [patent_app_number] => 11/555682 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/994/07994619.pdf [firstpage_image] =>[orig_patent_app_number] => 11555682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555682
Bridge stack integrated circuit package system Oct 31, 2006 Issued
Array ( [id] => 394300 [patent_doc_number] => 07297999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-20 [patent_title] => 'Semiconductor device with capacitors and its manufacture method' [patent_app_type] => utility [patent_app_number] => 11/589758 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 48 [patent_no_of_words] => 9181 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/297/07297999.pdf [firstpage_image] =>[orig_patent_app_number] => 11589758 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/589758
Semiconductor device with capacitors and its manufacture method Oct 30, 2006 Issued
Array ( [id] => 263708 [patent_doc_number] => 07569472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Method and apparatus of power ring positioning to minimize crosstalk' [patent_app_type] => utility [patent_app_number] => 11/590961 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6231 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/569/07569472.pdf [firstpage_image] =>[orig_patent_app_number] => 11590961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590961
Method and apparatus of power ring positioning to minimize crosstalk Oct 30, 2006 Issued
Array ( [id] => 393903 [patent_doc_number] => 07297596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Method of manufacturing a semiconductor device having a switching function' [patent_app_type] => utility [patent_app_number] => 11/552359 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 6098 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/297/07297596.pdf [firstpage_image] =>[orig_patent_app_number] => 11552359 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/552359
Method of manufacturing a semiconductor device having a switching function Oct 23, 2006 Issued
Array ( [id] => 5116815 [patent_doc_number] => 20070138529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'MIS capacitor and method of formation' [patent_app_type] => utility [patent_app_number] => 11/545481 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10350 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138529.pdf [firstpage_image] =>[orig_patent_app_number] => 11545481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/545481
MIS capacitor and method of formation Oct 10, 2006 Issued
Array ( [id] => 5578651 [patent_doc_number] => 20090173997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'MOSFET AND METHOD FOR MANUFACTURING MOSFET' [patent_app_type] => utility [patent_app_number] => 12/090451 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8501 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20090173997.pdf [firstpage_image] =>[orig_patent_app_number] => 12090451 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/090451
MOSFET and method for manufacturing MOSFET Oct 5, 2006 Issued
Array ( [id] => 4691222 [patent_doc_number] => 20080083992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'NOVEL BONDING AND PROBING PAD STRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/539498 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3831 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20080083992.pdf [firstpage_image] =>[orig_patent_app_number] => 11539498 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/539498
Bonding and probing pad structures Oct 5, 2006 Issued
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