Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20191162 [patent_doc_number] => 12402300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Semiconductor device having channel regions distributed on two opposite sides of a gate electrode [patent_app_type] => utility [patent_app_number] => 17/952262 [patent_app_country] => US [patent_app_date] => 2022-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 1008 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/952262
Semiconductor device having channel regions distributed on two opposite sides of a gate electrode Sep 24, 2022 Issued
Array ( [id] => 20191162 [patent_doc_number] => 12402300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Semiconductor device having channel regions distributed on two opposite sides of a gate electrode [patent_app_type] => utility [patent_app_number] => 17/952262 [patent_app_country] => US [patent_app_date] => 2022-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 1008 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/952262
Semiconductor device having channel regions distributed on two opposite sides of a gate electrode Sep 24, 2022 Issued
Array ( [id] => 19945323 [patent_doc_number] => 12317473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Semiconductor device having plurality of trenches with different depth [patent_app_type] => utility [patent_app_number] => 17/951077 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 0 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17951077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/951077
Semiconductor device having plurality of trenches with different depth Sep 21, 2022 Issued
Array ( [id] => 19973899 [patent_doc_number] => 12342532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Semiconductor structure and method for fabricating a device having source region with different doping types in horizontal direction [patent_app_type] => utility [patent_app_number] => 17/946063 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 2211 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946063 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946063
Semiconductor structure and method for fabricating a device having source region with different doping types in horizontal direction Sep 15, 2022 Issued
Array ( [id] => 20191165 [patent_doc_number] => 12402303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Semiconductor structure having a plurality of bit lines spaced apart from each other in a first direction and extend in a second direction [patent_app_type] => utility [patent_app_number] => 17/932276 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2342 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932276
Semiconductor structure having a plurality of bit lines spaced apart from each other in a first direction and extend in a second direction Sep 13, 2022 Issued
Array ( [id] => 20334411 [patent_doc_number] => 12464707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Semiconductor device having metal nitride gate doped with a low work function [patent_app_type] => utility [patent_app_number] => 17/939414 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939414
Semiconductor device having metal nitride gate doped with a low work function Sep 6, 2022 Issued
Array ( [id] => 18868029 [patent_doc_number] => 20230422466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/901853 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901853
Semiconductor structure for DRAM having a pillar lower electrode and formation method thereof Sep 1, 2022 Issued
Array ( [id] => 19487310 [patent_doc_number] => 12107035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Semiconductor device with a semiconductor die embedded between an extended substrate and a bottom substrate [patent_app_type] => utility [patent_app_number] => 17/897556 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897556
Semiconductor device with a semiconductor die embedded between an extended substrate and a bottom substrate Aug 28, 2022 Issued
Array ( [id] => 18516289 [patent_doc_number] => 20230232611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/892275 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892275 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892275
Semiconductor devices having a graphene pattern between the first conductive pattern and the bit line capping Aug 21, 2022 Issued
Array ( [id] => 18929287 [patent_doc_number] => 20240032291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => NON-VOLATILE MEMORY, FABRICATION AND CONTROL METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/888424 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888424 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888424
NON-VOLATILE MEMORY, FABRICATION AND CONTROL METHODS THEREOF Aug 14, 2022 Pending
Array ( [id] => 20113343 [patent_doc_number] => 12364099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Display panel having light shielding member with different thickness [patent_app_type] => utility [patent_app_number] => 17/886546 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 5726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886546
Display panel having light shielding member with different thickness Aug 11, 2022 Issued
Array ( [id] => 19945334 [patent_doc_number] => 12317484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Method for forming a first and a second transistors array having plurality of first and semiconductor pillars [patent_app_type] => utility [patent_app_number] => 17/879779 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2445 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879779
Method for forming a first and a second transistors array having plurality of first and semiconductor pillars Aug 2, 2022 Issued
Array ( [id] => 18812508 [patent_doc_number] => 20230386845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/815623 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815623
Semiconductor structure and manufacturing method using different ion implantation energy Jul 27, 2022 Issued
Array ( [id] => 18857610 [patent_doc_number] => 11855207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => FinFET structure and method with reduced fin buckling [patent_app_type] => utility [patent_app_number] => 17/876330 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876330 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876330
FinFET structure and method with reduced fin buckling Jul 27, 2022 Issued
Array ( [id] => 18379974 [patent_doc_number] => 20230155063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/873557 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873557
DISPLAY DEVICE Jul 25, 2022 Pending
Array ( [id] => 18593474 [patent_doc_number] => 11742386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Doping for semiconductor device with conductive feature [patent_app_type] => utility [patent_app_number] => 17/872452 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 40 [patent_no_of_words] => 9683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872452
Doping for semiconductor device with conductive feature Jul 24, 2022 Issued
Array ( [id] => 18008947 [patent_doc_number] => 20220367714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Integrated Assemblies having Transistors Configured for High-Voltage Applications, and Methods of Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 17/868683 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868683
Method of forming integrated assemblies having transistors configured for high-voltage applications Jul 18, 2022 Issued
Array ( [id] => 19844116 [patent_doc_number] => 12256531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Method for forming buried bit lines in the bit line trenchs [patent_app_type] => utility [patent_app_number] => 17/867432 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7581 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867432
Method for forming buried bit lines in the bit line trenchs Jul 17, 2022 Issued
Array ( [id] => 17993463 [patent_doc_number] => 20220359500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => ARRAY OF MULTI-STACK NANOSHEET STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/866066 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866066
Method of forming an array of multi-stack nanosheet structures having a dam structure isolating multi-stack transistors Jul 14, 2022 Issued
Array ( [id] => 18670066 [patent_doc_number] => 11776978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Solid-state image pickup device and electronic apparatus having a separation wall between the first photodiode and the second photodiode [patent_app_type] => utility [patent_app_number] => 17/863468 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 21624 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863468 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863468
Solid-state image pickup device and electronic apparatus having a separation wall between the first photodiode and the second photodiode Jul 12, 2022 Issued
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