Search

Hoai V. Pham

Examiner (ID: 18096)

Most Active Art Unit
2892
Art Unit(s)
2814, 2892, 2811
Total Applications
2250
Issued Applications
2043
Pending Applications
85
Abandoned Applications
160

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 881094 [patent_doc_number] => 07355232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Memory devices with dual-sided capacitors' [patent_app_type] => utility [patent_app_number] => 11/218578 [patent_app_country] => US [patent_app_date] => 2005-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 6008 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355232.pdf [firstpage_image] =>[orig_patent_app_number] => 11218578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218578
Memory devices with dual-sided capacitors Sep 5, 2005 Issued
Array ( [id] => 5588765 [patent_doc_number] => 20060038216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Formation of capacitor having a Fin structure' [patent_app_type] => utility [patent_app_number] => 11/216862 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7027 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20060038216.pdf [firstpage_image] =>[orig_patent_app_number] => 11216862 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216862
Formation of capacitor having a Fin structure Aug 30, 2005 Issued
Array ( [id] => 5903463 [patent_doc_number] => 20060046388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Nonvolatile semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/214247 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8359 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046388.pdf [firstpage_image] =>[orig_patent_app_number] => 11214247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214247
Nonvolatile semiconductor device and method of fabricating the same Aug 28, 2005 Issued
Array ( [id] => 5727057 [patent_doc_number] => 20060057817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Semiconductor device, its manufacture method and electronic component unit' [patent_app_type] => utility [patent_app_number] => 11/204527 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10769 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20060057817.pdf [firstpage_image] =>[orig_patent_app_number] => 11204527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204527
Semiconductor device, its manufacture method and electronic component unit Aug 15, 2005 Issued
Array ( [id] => 4919343 [patent_doc_number] => 20080067655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Device Comprising an Encapsulated Microsystem and Production Method Thereof' [patent_app_type] => utility [patent_app_number] => 11/573207 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2833 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067655.pdf [firstpage_image] =>[orig_patent_app_number] => 11573207 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/573207
Device comprising an encapsulated microsystem and production method thereof Aug 9, 2005 Issued
Array ( [id] => 5738606 [patent_doc_number] => 20060008997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Atomic layer deposition of interpoly oxides in a non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 11/197562 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3995 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20060008997.pdf [firstpage_image] =>[orig_patent_app_number] => 11197562 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197562
Atomic layer deposition of interpoly oxides in a non-volatile memory device Aug 3, 2005 Abandoned
Array ( [id] => 5765874 [patent_doc_number] => 20050263876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/196038 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2855 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20050263876.pdf [firstpage_image] =>[orig_patent_app_number] => 11196038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196038
Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit Aug 1, 2005 Issued
Array ( [id] => 896329 [patent_doc_number] => 07342305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-11 [patent_title] => 'Thermally enhanced cavity-down integrated circuit package' [patent_app_type] => utility [patent_app_number] => 11/191678 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 2445 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/342/07342305.pdf [firstpage_image] =>[orig_patent_app_number] => 11191678 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/191678
Thermally enhanced cavity-down integrated circuit package Jul 27, 2005 Issued
Array ( [id] => 7206083 [patent_doc_number] => 20050258465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Semiconductor memory device including multi-layer gate structure' [patent_app_type] => utility [patent_app_number] => 11/190619 [patent_app_country] => US [patent_app_date] => 2005-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12111 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20050258465.pdf [firstpage_image] =>[orig_patent_app_number] => 11190619 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/190619
Semiconductor memory device including multi-layer gate structure Jul 26, 2005 Issued
Array ( [id] => 627344 [patent_doc_number] => 07135729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Semiconductor memory device including multi-layer gate structure' [patent_app_type] => utility [patent_app_number] => 11/190585 [patent_app_country] => US [patent_app_date] => 2005-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 35 [patent_no_of_words] => 12146 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135729.pdf [firstpage_image] =>[orig_patent_app_number] => 11190585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/190585
Semiconductor memory device including multi-layer gate structure Jul 26, 2005 Issued
Array ( [id] => 5242317 [patent_doc_number] => 20070020812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Circuit board structure integrated with semiconductor chip and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/184979 [patent_app_country] => US [patent_app_date] => 2005-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3332 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020812.pdf [firstpage_image] =>[orig_patent_app_number] => 11184979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/184979
Circuit board structure integrated with semiconductor chip and method of fabricating the same Jul 19, 2005 Abandoned
Array ( [id] => 509618 [patent_doc_number] => 07195964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/182875 [patent_app_country] => US [patent_app_date] => 2005-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 6874 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/195/07195964.pdf [firstpage_image] =>[orig_patent_app_number] => 11182875 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/182875
Fabrication of dielectric on a gate surface to insulate the gate from another element of an integrated circuit Jul 13, 2005 Issued
Array ( [id] => 582963 [patent_doc_number] => 07445955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Multichip module package and fabrication method' [patent_app_type] => utility [patent_app_number] => 11/160837 [patent_app_country] => US [patent_app_date] => 2005-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3104 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/445/07445955.pdf [firstpage_image] =>[orig_patent_app_number] => 11160837 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160837
Multichip module package and fabrication method Jul 11, 2005 Issued
Array ( [id] => 646380 [patent_doc_number] => 07119406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Semiconductor integrated circuit device having deposited layer for gate insulation' [patent_app_type] => utility [patent_app_number] => 11/178375 [patent_app_country] => US [patent_app_date] => 2005-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 48 [patent_no_of_words] => 14873 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119406.pdf [firstpage_image] =>[orig_patent_app_number] => 11178375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/178375
Semiconductor integrated circuit device having deposited layer for gate insulation Jul 11, 2005 Issued
Array ( [id] => 889177 [patent_doc_number] => 07348672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Interconnects with improved reliability' [patent_app_type] => utility [patent_app_number] => 11/175329 [patent_app_country] => US [patent_app_date] => 2005-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2006 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/348/07348672.pdf [firstpage_image] =>[orig_patent_app_number] => 11175329 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/175329
Interconnects with improved reliability Jul 6, 2005 Issued
Array ( [id] => 5628732 [patent_doc_number] => 20060145200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'GATE STRUCTURE OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/174788 [patent_app_country] => US [patent_app_date] => 2005-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2064 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145200.pdf [firstpage_image] =>[orig_patent_app_number] => 11174788 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/174788
Gate structure of a semiconductor device Jul 4, 2005 Issued
Array ( [id] => 7067024 [patent_doc_number] => 20050242406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Nonplanar device with stress incorporation layer and method of fabrication' [patent_app_type] => utility [patent_app_number] => 11/173443 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8149 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20050242406.pdf [firstpage_image] =>[orig_patent_app_number] => 11173443 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/173443
Nonplanar device with stress incorporation layer and method of fabrication Jun 29, 2005 Issued
Array ( [id] => 1076963 [patent_doc_number] => 07615476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages' [patent_app_type] => utility [patent_app_number] => 11/173939 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5578 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615476.pdf [firstpage_image] =>[orig_patent_app_number] => 11173939 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/173939
Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages Jun 29, 2005 Issued
Array ( [id] => 6923447 [patent_doc_number] => 20050236702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Semiconductor package for a large die' [patent_app_type] => utility [patent_app_number] => 11/169850 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6157 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20050236702.pdf [firstpage_image] =>[orig_patent_app_number] => 11169850 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/169850
Semiconductor package for a large die Jun 27, 2005 Issued
Array ( [id] => 7228807 [patent_doc_number] => 20050269678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Package for sealing an integrated circuit die' [patent_app_type] => utility [patent_app_number] => 11/169276 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2981 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20050269678.pdf [firstpage_image] =>[orig_patent_app_number] => 11169276 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/169276
Package for sealing an integrated circuit die Jun 27, 2005 Issued
Menu