
Hoai V. Pham
Examiner (ID: 18096)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2814, 2892, 2811 |
| Total Applications | 2250 |
| Issued Applications | 2043 |
| Pending Applications | 85 |
| Abandoned Applications | 160 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 881094
[patent_doc_number] => 07355232
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[patent_kind] => B2
[patent_issue_date] => 2008-04-08
[patent_title] => 'Memory devices with dual-sided capacitors'
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[patent_app_country] => US
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Array
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[patent_issue_date] => 2006-02-23
[patent_title] => 'Formation of capacitor having a Fin structure'
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Array
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[patent_title] => 'Nonvolatile semiconductor device and method of fabricating the same'
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Array
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[patent_title] => 'Semiconductor device, its manufacture method and electronic component unit'
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Array
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[patent_title] => 'Device Comprising an Encapsulated Microsystem and Production Method Thereof'
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Array
(
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[patent_title] => 'Atomic layer deposition of interpoly oxides in a non-volatile memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/197562 | Atomic layer deposition of interpoly oxides in a non-volatile memory device | Aug 3, 2005 | Abandoned |
Array
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[patent_title] => 'Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit'
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Array
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[patent_doc_number] => 07342305
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[patent_issue_date] => 2008-03-11
[patent_title] => 'Thermally enhanced cavity-down integrated circuit package'
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Array
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[patent_doc_number] => 20050258465
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[patent_title] => 'Semiconductor memory device including multi-layer gate structure'
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Array
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[patent_title] => 'Semiconductor memory device including multi-layer gate structure'
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Array
(
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[patent_title] => 'Circuit board structure integrated with semiconductor chip and method of fabricating the same'
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Array
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Array
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Array
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Array
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