Hoai V. Pham

Array ( [id] => 7039563 [patent_doc_number] => 20050158962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Semiconductor device and process for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/078519 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12588 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20050158962.pdf [firstpage_image] =>[orig_patent_app_number] => 11078519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7036838 [patent_doc_number] => 20050156272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Semiconductor devices having storage nodes' [patent_app_type] => utility [patent_app_number] => 11/077838 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7406 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156272.pdf [firstpage_image] =>[orig_patent_app_number] => 11077838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7036799 [patent_doc_number] => 20050156233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Stacked gate flash memory device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/076499 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3904 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156233.pdf [firstpage_image] =>[orig_patent_app_number] => 11076499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6958609 [patent_doc_number] => 20050214979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Semiconductor package and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/074747 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6348 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20050214979.pdf [firstpage_image] =>[orig_patent_app_number] => 11074747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6966641 [patent_doc_number] => 20050233538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Integrated dynamic memory cell and method for fabricating it' [patent_app_type] => utility [patent_app_number] => 11/071527 [patent_app_country] => US [patent_app_date] => 2005-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1824 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20050233538.pdf [firstpage_image] =>[orig_patent_app_number] => 11071527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6981151 [patent_doc_number] => 20050151219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Diode and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/072868 [patent_app_country] => US [patent_app_date] => 2005-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15896 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20050151219.pdf [firstpage_image] =>[orig_patent_app_number] => 11072868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7002339 [patent_doc_number] => 20050167652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Gate-induced strain for MOS performance improvement' [patent_app_type] => utility [patent_app_number] => 11/070365 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6019 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20050167652.pdf [firstpage_image] =>[orig_patent_app_number] => 11070365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 62701 [patent_doc_number] => 07763477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Fabrication of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/593107 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4888 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763477.pdf [firstpage_image] =>[orig_patent_app_number] => 10593107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7236418 [patent_doc_number] => 20050139959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Intralevel decoupling capacitor, method of manufacture and testing circuit of the same' [patent_app_type] => utility [patent_app_number] => 11/066738 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3734 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139959.pdf [firstpage_image] =>[orig_patent_app_number] => 11066738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7036755 [patent_doc_number] => 20050156196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Local interconnect for integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/058498 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4006 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156196.pdf [firstpage_image] =>[orig_patent_app_number] => 11058498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 630747 [patent_doc_number] => 07132708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Semiconductor memory device having self-aligned contacts and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/054593 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5971 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132708.pdf [firstpage_image] =>[orig_patent_app_number] => 11054593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6994052 [patent_doc_number] => 20050133828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Corner protection to reduce wrap around' [patent_app_type] => utility [patent_app_number] => 11/048668 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20050133828.pdf [firstpage_image] =>[orig_patent_app_number] => 11048668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6996795 [patent_doc_number] => 20050136573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Method of making direct contact on gate by using dielectric stop layer' [patent_app_type] => utility [patent_app_number] => 11/045958 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1579 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20050136573.pdf [firstpage_image] =>[orig_patent_app_number] => 11045958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 928735 [patent_doc_number] => 07315045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Sapphire/gallium nitride laminate having reduced bending deformation' [patent_app_type] => utility [patent_app_number] => 11/045688 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1887 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315045.pdf [firstpage_image] =>[orig_patent_app_number] => 11045688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5040720 [patent_doc_number] => 20070093002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Electric appliance, semiconductor device, and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/579800 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 26533 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20070093002.pdf [firstpage_image] =>[orig_patent_app_number] => 10579800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7169078 [patent_doc_number] => 20050121719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Semiconductor device with elevated source/drain structure and its manufacture method' [patent_app_type] => utility [patent_app_number] => 11/029384 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2987 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121719.pdf [firstpage_image] =>[orig_patent_app_number] => 11029384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6981105 [patent_doc_number] => 20050151173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Semiconductor device and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/022809 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4352 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20050151173.pdf [firstpage_image] =>[orig_patent_app_number] => 11022809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7236113 [patent_doc_number] => 20050139921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/019179 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139921.pdf [firstpage_image] =>[orig_patent_app_number] => 11019179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6918221 [patent_doc_number] => 20050095782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Lower electrode contact structure and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/000943 [patent_app_country] => US [patent_app_date] => 2004-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4068 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20050095782.pdf [firstpage_image] =>[orig_patent_app_number] => 11000943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6915512 [patent_doc_number] => 20050093073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Low voltage NMOS-based electrostatic discharge lamp' [patent_app_type] => utility [patent_app_number] => 11/000584 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2711 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093073.pdf [firstpage_image] =>[orig_patent_app_number] => 11000584 [rel_patent_id] =>[rel_patent_doc_number] =>)