Howard W Britton

Array ( [id] => 586335 [patent_doc_number] => 07467260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Method and apparatus to purge remote node cache lines to support hot node replace in a computing system' [patent_app_type] => utility [patent_app_number] => 10/961746 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6493 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/467/07467260.pdf [firstpage_image] =>[orig_patent_app_number] => 10961746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5717148 [patent_doc_number] => 20060080511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Enhanced bus transactions for efficient support of a remote cache directory copy' [patent_app_type] => utility [patent_app_number] => 10/961742 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4460 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20060080511.pdf [firstpage_image] =>[orig_patent_app_number] => 10961742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 374882 [patent_doc_number] => 07475190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Direct access of cache lock set data without backing memory' [patent_app_type] => utility [patent_app_number] => 10/961752 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3465 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475190.pdf [firstpage_image] =>[orig_patent_app_number] => 10961752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 388535 [patent_doc_number] => 07305524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Snoop filter directory mechanism in coherency shared memory system' [patent_app_type] => utility [patent_app_number] => 10/961749 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5527 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305524.pdf [firstpage_image] =>[orig_patent_app_number] => 10961749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 258107 [patent_doc_number] => 07577794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Low latency coherency protocol for a multi-chip multiprocessor system' [patent_app_type] => utility [patent_app_number] => 10/961751 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4984 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577794.pdf [firstpage_image] =>[orig_patent_app_number] => 10961751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7140302 [patent_doc_number] => 20050182769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Storage system, computer system and a method of establishing volume attribute' [patent_app_type] => utility [patent_app_number] => 10/962377 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10393 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20050182769.pdf [firstpage_image] =>[orig_patent_app_number] => 10962377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 231436 [patent_doc_number] => 07603528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Memory device verification of multiple write operations' [patent_app_type] => utility [patent_app_number] => 10/961745 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6802 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/603/07603528.pdf [firstpage_image] =>[orig_patent_app_number] => 10961745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 421305 [patent_doc_number] => 07278000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Data migration with worm guarantee' [patent_app_type] => utility [patent_app_number] => 10/960053 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16184 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/278/07278000.pdf [firstpage_image] =>[orig_patent_app_number] => 10960053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 388517 [patent_doc_number] => 07305516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Multi-port memory device with precharge control' [patent_app_type] => utility [patent_app_number] => 10/877887 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 10275 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305516.pdf [firstpage_image] =>[orig_patent_app_number] => 10877887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6979582 [patent_doc_number] => 20050289300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Disable write back on atomic reserved line in a small cache system' [patent_app_type] => utility [patent_app_number] => 10/875953 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3125 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289300.pdf [firstpage_image] =>[orig_patent_app_number] => 10875953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4996053 [patent_doc_number] => 20070011398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Method and device for transferring data between a main memory and a storage device' [patent_app_type] => utility [patent_app_number] => 10/557347 [patent_app_country] => US [patent_app_date] => 2004-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6494 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011398.pdf [firstpage_image] =>[orig_patent_app_number] => 10557347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7049902 [patent_doc_number] => 20050185789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Forestalling actions that otherwise would defeat access-control mechanism for volume' [patent_app_type] => utility [patent_app_number] => 10/767429 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13244 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20050185789.pdf [firstpage_image] =>[orig_patent_app_number] => 10767429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7036631 [patent_doc_number] => 20050034125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Multiple virtual devices' [patent_app_type] => utility [patent_app_number] => 10/634278 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6768 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20050034125.pdf [firstpage_image] =>[orig_patent_app_number] => 10634278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7298112 [patent_doc_number] => 20040125808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Multi-priority encoder' [patent_app_type] => new [patent_app_number] => 10/330204 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3347 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20040125808.pdf [firstpage_image] =>[orig_patent_app_number] => 10330204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7524962 [patent_doc_number] => 08028132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Collision handling apparatus and method' [patent_app_type] => utility [patent_app_number] => 10/498423 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5344 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028132.pdf [firstpage_image] =>[orig_patent_app_number] => 10498423 [rel_patent_id] =>[rel_patent_doc_number] =>)