Search

Howard Weiss

Examiner (ID: 16064)

Most Active Art Unit
2814
Art Unit(s)
2814, 2508
Total Applications
950
Issued Applications
632
Pending Applications
10
Abandoned Applications
309

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7773089 [patent_doc_number] => 20120037985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'APPARATUS WITH CAPACITIVE COUPLING AND ASSOCIATED METHODS' [patent_app_type] => utility [patent_app_number] => 12/857277 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4823 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20120037985.pdf [firstpage_image] =>[orig_patent_app_number] => 12857277 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/857277
APPARATUS WITH CAPACITIVE COUPLING AND ASSOCIATED METHODS Aug 15, 2010 Abandoned
Array ( [id] => 7773098 [patent_doc_number] => 20120037991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'Silicon on Insulator Field Effect Device' [patent_app_type] => utility [patent_app_number] => 12/857022 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20120037991.pdf [firstpage_image] =>[orig_patent_app_number] => 12857022 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/857022
Silicon on Insulator Field Effect Device Aug 15, 2010 Abandoned
Array ( [id] => 9710663 [patent_doc_number] => 08835231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Methods of forming contacts for nanowire field effect transistors' [patent_app_type] => utility [patent_app_number] => 12/856718 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12856718 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856718
Methods of forming contacts for nanowire field effect transistors Aug 15, 2010 Issued
Array ( [id] => 7773111 [patent_doc_number] => 20120037999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'DIFFERENTIAL STOICHIOMETRIES BY INFUSION THRU GCIB FOR MULTIPLE WORK FUNCTION METAL GATE CMOS' [patent_app_type] => utility [patent_app_number] => 12/857108 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3222 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20120037999.pdf [firstpage_image] =>[orig_patent_app_number] => 12857108 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/857108
DIFFERENTIAL STOICHIOMETRIES BY INFUSION THRU GCIB FOR MULTIPLE WORK FUNCTION METAL GATE CMOS Aug 15, 2010 Abandoned
Array ( [id] => 7773124 [patent_doc_number] => 20120038008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'Field Effect Transistor Device with Self-Aligned Junction and Spacer' [patent_app_type] => utility [patent_app_number] => 12/857017 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2243 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20120038008.pdf [firstpage_image] =>[orig_patent_app_number] => 12857017 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/857017
Field Effect Transistor Device with Self-Aligned Junction and Spacer Aug 15, 2010 Abandoned
Array ( [id] => 7577385 [patent_doc_number] => 20110291267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'Semiconductor wafer structure and multi-chip stack structure' [patent_app_type] => utility [patent_app_number] => 12/856754 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13092 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291267.pdf [firstpage_image] =>[orig_patent_app_number] => 12856754 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856754
Semiconductor wafer structure and multi-chip stack structure Aug 15, 2010 Abandoned
Array ( [id] => 6067784 [patent_doc_number] => 20110042767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'FILTERS IN AN IMAGE SENSOR' [patent_app_type] => utility [patent_app_number] => 12/857287 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2116 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20110042767.pdf [firstpage_image] =>[orig_patent_app_number] => 12857287 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/857287
FILTERS IN AN IMAGE SENSOR Aug 15, 2010 Abandoned
Array ( [id] => 9778657 [patent_doc_number] => 08853865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Semiconductor device with overlapped lead terminals' [patent_app_type] => utility [patent_app_number] => 12/856664 [patent_app_country] => US [patent_app_date] => 2010-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 106 [patent_no_of_words] => 26084 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12856664 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856664
Semiconductor device with overlapped lead terminals Aug 14, 2010 Issued
Array ( [id] => 8701451 [patent_doc_number] => 08394672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Method of manufacturing and assembling semiconductor chips with offset pads' [patent_app_type] => utility [patent_app_number] => 12/856632 [patent_app_country] => US [patent_app_date] => 2010-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5790 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12856632 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856632
Method of manufacturing and assembling semiconductor chips with offset pads Aug 13, 2010 Issued
Array ( [id] => 6169975 [patent_doc_number] => 20110175183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'INTEGRATED PLASMONIC LENS PHOTODETECTOR' [patent_app_type] => utility [patent_app_number] => 12/856506 [patent_app_country] => US [patent_app_date] => 2010-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3324 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20110175183.pdf [firstpage_image] =>[orig_patent_app_number] => 12856506 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856506
INTEGRATED PLASMONIC LENS PHOTODETECTOR Aug 12, 2010 Abandoned
Array ( [id] => 6493947 [patent_doc_number] => 20100200859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'THIN FILM TRANSISTOR ARRAY PANEL FOR X-RAY DETECTOR' [patent_app_type] => utility [patent_app_number] => 12/762485 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2566 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20100200859.pdf [firstpage_image] =>[orig_patent_app_number] => 12762485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762485
Thin film transistor array panel for x-ray detector Apr 18, 2010 Issued
Array ( [id] => 6316011 [patent_doc_number] => 20100195267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'POLYMER MEMORY AND METHOD OF ITS FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/757731 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195267.pdf [firstpage_image] =>[orig_patent_app_number] => 12757731 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757731
POLYMER MEMORY AND METHOD OF ITS FABRICATION Apr 8, 2010 Abandoned
Array ( [id] => 4517354 [patent_doc_number] => 07910927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Thin film transistor array panel with common bars of different widths' [patent_app_type] => utility [patent_app_number] => 12/715319 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 6218 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/910/07910927.pdf [firstpage_image] =>[orig_patent_app_number] => 12715319 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715319
Thin film transistor array panel with common bars of different widths Feb 28, 2010 Issued
Array ( [id] => 6583476 [patent_doc_number] => 20100129992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/695759 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13282 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20100129992.pdf [firstpage_image] =>[orig_patent_app_number] => 12695759 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695759
Method for manufacturing a semiconductor device having a III-V nitride semiconductor Jan 27, 2010 Issued
Array ( [id] => 6419044 [patent_doc_number] => 20100167479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'EMBEDDED TRAP DIRECT TUNNEL NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/694789 [patent_app_country] => US [patent_app_date] => 2010-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3094 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20100167479.pdf [firstpage_image] =>[orig_patent_app_number] => 12694789 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/694789
Method of making an embedded trap direct tunnel non-volatile memory Jan 26, 2010 Issued
Array ( [id] => 6550053 [patent_doc_number] => 20100127402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'Interconnect System without Through-Holes' [patent_app_type] => utility [patent_app_number] => 12/692974 [patent_app_country] => US [patent_app_date] => 2010-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5734 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20100127402.pdf [firstpage_image] =>[orig_patent_app_number] => 12692974 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/692974
Interconnect System without Through-Holes Jan 24, 2010 Abandoned
Array ( [id] => 7490560 [patent_doc_number] => 08030211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Methods for forming bit line contacts and bit lines during the formation of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/629153 [patent_app_country] => US [patent_app_date] => 2009-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 60 [patent_no_of_words] => 5570 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030211.pdf [firstpage_image] =>[orig_patent_app_number] => 12629153 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/629153
Methods for forming bit line contacts and bit lines during the formation of a semiconductor device Dec 1, 2009 Issued
Array ( [id] => 7660198 [patent_doc_number] => 20110309467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/141332 [patent_app_country] => US [patent_app_date] => 2009-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6119 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20110309467.pdf [firstpage_image] =>[orig_patent_app_number] => 13141332 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/141332
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Nov 24, 2009 Abandoned
Array ( [id] => 6240394 [patent_doc_number] => 20100133698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/619063 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5402 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20100133698.pdf [firstpage_image] =>[orig_patent_app_number] => 12619063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619063
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Nov 15, 2009 Abandoned
Array ( [id] => 6279913 [patent_doc_number] => 20100155728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'EPITAXIAL WAFER AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/619043 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2420 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155728.pdf [firstpage_image] =>[orig_patent_app_number] => 12619043 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619043
EPITAXIAL WAFER AND METHOD FOR FABRICATING THE SAME Nov 15, 2009 Abandoned
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