
Howard Weiss
Examiner (ID: 2081)
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2508, 2814 |
| Total Applications | 950 |
| Issued Applications | 632 |
| Pending Applications | 10 |
| Abandoned Applications | 309 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6279913
[patent_doc_number] => 20100155728
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-24
[patent_title] => 'EPITAXIAL WAFER AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/619043
[patent_app_country] => US
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[pdf_file] => publications/A1/0155/20100155728.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/619043 | EPITAXIAL WAFER AND METHOD FOR FABRICATING THE SAME | Nov 15, 2009 | Abandoned |
Array
(
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[patent_doc_number] => 20100133698
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[patent_kind] => A1
[patent_issue_date] => 2010-06-03
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
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Array
(
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[patent_title] => 'Semiconductor Optoelectronic Structure and the Fabricating Method Thereof'
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[firstpage_image] =>[orig_patent_app_number] => 12618774
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/618774 | Semiconductor optoelectronic structure | Nov 14, 2009 | Issued |
Array
(
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[patent_doc_number] => 20110115070
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-19
[patent_title] => 'Semiconductor Device and Method of Forming Protective Material Between Semiconductor Die Stacked on Semiconductor Wafer to Reduce Defects During Singulation'
[patent_app_type] => utility
[patent_app_number] => 12/617877
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[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/617877 | Method of forming protective material between semiconductor die stacked on semiconductor wafer to reduce defects during singulation | Nov 12, 2009 | Issued |
Array
(
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[patent_doc_number] => 20100187656
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[patent_kind] => A1
[patent_issue_date] => 2010-07-29
[patent_title] => 'Bipolar Junction Transistors and Methods of Fabrication Thereof'
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[firstpage_image] =>[orig_patent_app_number] => 12618425
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/618425 | Bipolar junction transistors having a fin | Nov 12, 2009 | Issued |
Array
(
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[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING CHARGE STORAGE LAYERS AND MANUFACTURING METHOD THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/618035 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING CHARGE STORAGE LAYERS AND MANUFACTURING METHOD THEREOF | Nov 12, 2009 | Abandoned |
Array
(
[id] => 8270809
[patent_doc_number] => 08212308
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[patent_kind] => B2
[patent_issue_date] => 2012-07-03
[patent_title] => 'Nonvolatile semiconductor flash memory'
[patent_app_type] => utility
[patent_app_number] => 12/618058
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/618058 | Nonvolatile semiconductor flash memory | Nov 12, 2009 | Issued |
Array
(
[id] => 6478595
[patent_doc_number] => 20100213548
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[patent_kind] => A1
[patent_issue_date] => 2010-08-26
[patent_title] => 'Semiconductor Devices with Low Junction Capacitances and Methods of Fabrication Thereof'
[patent_app_type] => utility
[patent_app_number] => 12/618505
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/618505 | Methods of fabrication of semiconductor devices with low capacitance | Nov 12, 2009 | Issued |
Array
(
[id] => 6518921
[patent_doc_number] => 20100123206
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[patent_issue_date] => 2010-05-20
[patent_title] => 'METHODS OF FABRICATING FIELD EFFECT TRANSISTORS INCLUDING TITANIUM NITRIDE GATES OVER PARTIALLY NITRIDED OXIDE AND DEVICES SO FABRICATED'
[patent_app_type] => utility
[patent_app_number] => 12/617938
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[pdf_file] => publications/A1/0123/20100123206.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/617938 | METHODS OF FABRICATING FIELD EFFECT TRANSISTORS INCLUDING TITANIUM NITRIDE GATES OVER PARTIALLY NITRIDED OXIDE AND DEVICES SO FABRICATED | Nov 12, 2009 | Abandoned |
Array
(
[id] => 6519106
[patent_doc_number] => 20100123222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-20
[patent_title] => 'PROCESS FOR FABRICATING A CHARGE STORAGE LAYER OF A MEMORY CELL'
[patent_app_type] => utility
[patent_app_number] => 12/618516
[patent_app_country] => US
[patent_app_date] => 2009-11-13
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[pdf_file] => publications/A1/0123/20100123222.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/618516 | Process for fabricating a charge storage layer of a memory cell | Nov 12, 2009 | Issued |
Array
(
[id] => 6548086
[patent_doc_number] => 20100127249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-27
[patent_title] => 'ELECTROPHORETIC DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/618405
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/618405 | Method for fabricating an electrophoretic display having simplified process | Nov 12, 2009 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/618515 | MOS POWER TRANSISTOR | Nov 12, 2009 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/606876 | Semiconductor component with stress-absorbing semiconductor layer | Oct 26, 2009 | Issued |
Array
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[patent_title] => 'LIGHT-EMITTING ARRANGEMENT'
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Array
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[patent_title] => 'LAYERED STRUCTURE AND ELECTRON DEVICE THAT USES SUCH A LAYERED STRUCTURE, FABRICATION PROCESS THEREOF, ELECTRON DEVICE ARRAY AND DISPLAY APPARATUS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/548208 | Layered structure, electron device, and an electron device array having a variable wettability layer and semiconductor layer formed thereon | Aug 25, 2009 | Issued |
Array
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Array
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Array
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