Search

Hsien Ming Lee

Examiner (ID: 17169, Phone: (571)272-1863 , Office: P/2823 )

Most Active Art Unit
2823
Art Unit(s)
2814, 2823
Total Applications
2377
Issued Applications
2182
Pending Applications
27
Abandoned Applications
178

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17247042 [patent_doc_number] => 20210366787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => METAL CONNECTIONS AND ROUTING FOR ADVANCED 3D LAYOUT DESIGNS [patent_app_type] => utility [patent_app_number] => 17/115122 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115122
Metal connections and routing for advanced 3D layout designs Dec 7, 2020 Issued
Array ( [id] => 16723918 [patent_doc_number] => 20210091065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => Semiconductor Device with Multiple Polarity Groups [patent_app_type] => utility [patent_app_number] => 17/113204 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113204 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113204
Semiconductor device with multiple polarity groups Dec 6, 2020 Issued
Array ( [id] => 16723944 [patent_doc_number] => 20210091091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR DEVICE HAVING A BUTTED CONTACT, METHOD OF FORMING AND METHOD OF USING [patent_app_type] => utility [patent_app_number] => 17/111074 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111074
Semiconductor device having a butted contact, method of forming and method of using Dec 2, 2020 Issued
Array ( [id] => 17660805 [patent_doc_number] => 20220181270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MEMORY DEVICE INCLUDING SUPPORT STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/111117 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111117
Memory device including support structures Dec 2, 2020 Issued
Array ( [id] => 16827760 [patent_doc_number] => 20210143053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => STRUCTURES FOR RADIOFREQUENCY APPLICATIONS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/109978 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109978
Structures for radiofrequency applications and related methods Dec 1, 2020 Issued
Array ( [id] => 18174946 [patent_doc_number] => 11574663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Data latch circuit and semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/109853 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 13572 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109853
Data latch circuit and semiconductor memory device Dec 1, 2020 Issued
Array ( [id] => 17431704 [patent_doc_number] => 20220059413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => OPTIMUM HIGH DENSITY 3D DEVICE LAYOUT AND METHOD OF FABRICATION [patent_app_type] => utility [patent_app_number] => 17/108525 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108525
Optimum high density 3D device layout and method of fabrication Nov 30, 2020 Issued
Array ( [id] => 17758178 [patent_doc_number] => 11398477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/106572 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 9708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106572
Semiconductor device and method Nov 29, 2020 Issued
Array ( [id] => 17630673 [patent_doc_number] => 20220165688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => ACTIVE PROTECTION CIRCUITS FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/103447 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103447
Active protection circuits for semiconductor devices Nov 23, 2020 Issued
Array ( [id] => 16712953 [patent_doc_number] => 20210080100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => HERMETICALLY SEALED LED LIGHT AND METHOD FOR MANUFACTURING A HERMETICALLY SEALED LED LIGHT [patent_app_type] => utility [patent_app_number] => 17/103217 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103217
Hermetically sealed LED light and method for manufacturing a hermetically sealed LED light Nov 23, 2020 Issued
Array ( [id] => 17145331 [patent_doc_number] => 20210313344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/101401 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101401
Semiconductor memory device and method of fabricating the same Nov 22, 2020 Issued
Array ( [id] => 16873728 [patent_doc_number] => 20210167195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => Vertical Power Semiconductor Device, Semiconductor Wafer or Bare-Die Arrangement, Carrier, and Method of Manufacturing a Vertical Power Semiconductor Device [patent_app_type] => utility [patent_app_number] => 17/100189 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100189
Vertical power semiconductor device, semiconductor wafer or bare-die arrangement, carrier, and method of manufacturing a vertical power semiconductor device Nov 19, 2020 Issued
Array ( [id] => 17278011 [patent_doc_number] => 20210384209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/090735 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090735 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/090735
Method of manufacturing semiconductor device Nov 4, 2020 Issued
Array ( [id] => 16808138 [patent_doc_number] => 20210130691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => COMPOSITION FOR ETCHING [patent_app_type] => utility [patent_app_number] => 17/087628 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087628
Composition for etching Nov 2, 2020 Issued
Array ( [id] => 16657642 [patent_doc_number] => 20210054278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => COMPOSITION FOR ETCHING [patent_app_type] => utility [patent_app_number] => 17/087633 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087633
Composition for etching Nov 2, 2020 Issued
Array ( [id] => 16808139 [patent_doc_number] => 20210130692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => COMPOSITION FOR ETCHING [patent_app_type] => utility [patent_app_number] => 17/087636 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087636 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087636
Composition for etching Nov 2, 2020 Issued
Array ( [id] => 17583232 [patent_doc_number] => 20220140087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => ELECTRONIC DEVICE WITH GALLIUM NITRIDE TRANSISTORS AND METHOD OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 17/085558 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085558
Electronic device with gallium nitride transistors and method of making same Oct 29, 2020 Issued
Array ( [id] => 17347206 [patent_doc_number] => 20220013537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES WITH CHANNEL STRUCTURES HAVING PLUM BLOSSOM SHAPE [patent_app_type] => utility [patent_app_number] => 17/085366 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085366 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085366
Methods for forming three-dimensional memory devices with channel structures having plum blossom shape Oct 29, 2020 Issued
Array ( [id] => 16625021 [patent_doc_number] => 20210043674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SOLID-STATE IMAGE PICKUP ELEMENT AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/076498 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076498 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076498
Solid-state image pickup element and electronic apparatus Oct 20, 2020 Issued
Array ( [id] => 17529928 [patent_doc_number] => 11302627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => On-chip capacitors in three-dimensional semiconductor devices and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/076624 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076624 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076624
On-chip capacitors in three-dimensional semiconductor devices and methods for forming the same Oct 20, 2020 Issued
Menu