Search

Hsien Ming Lee

Examiner (ID: 17169, Phone: (571)272-1863 , Office: P/2823 )

Most Active Art Unit
2823
Art Unit(s)
2814, 2823
Total Applications
2377
Issued Applications
2182
Pending Applications
27
Abandoned Applications
178

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17848116 [patent_doc_number] => 11437503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/020471 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 6068 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/020471
Semiconductor device Sep 13, 2020 Issued
Array ( [id] => 17772596 [patent_doc_number] => 11404550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/017332 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 16022 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017332 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017332
Semiconductor device and method for manufacturing the same Sep 9, 2020 Issued
Array ( [id] => 16544915 [patent_doc_number] => 20200411330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 17/015637 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/015637
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM Sep 8, 2020 Abandoned
Array ( [id] => 18137337 [patent_doc_number] => 11563026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/010454 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 64 [patent_no_of_words] => 13122 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010454
Semiconductor storage device Sep 1, 2020 Issued
Array ( [id] => 16512735 [patent_doc_number] => 20200391993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => VERTICAL SHEAR WELD WAFER BONDING [patent_app_type] => utility [patent_app_number] => 17/008133 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008133
VERTICAL SHEAR WELD WAFER BONDING Aug 30, 2020 Abandoned
Array ( [id] => 17516952 [patent_doc_number] => 11296113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Three-dimensional memory device with vertical field effect transistors and method of making thereof [patent_app_type] => utility [patent_app_number] => 17/007761 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 47 [patent_no_of_words] => 12748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007761 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007761
Three-dimensional memory device with vertical field effect transistors and method of making thereof Aug 30, 2020 Issued
Array ( [id] => 17448293 [patent_doc_number] => 20220068798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => PACKAGE AND SUBSTRATE COMPRISING INTERCONNECTS WITH SEMI-CIRCULAR PLANAR SHAPE AND/OR TRAPEZOID PLANAR SHAPE [patent_app_type] => utility [patent_app_number] => 17/002615 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002615
Package and substrate comprising interconnects with semi-circular planar shape and/or trapezoid planar shape Aug 24, 2020 Issued
Array ( [id] => 17431850 [patent_doc_number] => 20220059559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES AND MEMORY DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/000754 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17000754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/000754
Methods of forming microelectronic devices and memory devices, and related microelectronic devices, memory devices, and electronic systems Aug 23, 2020 Issued
Array ( [id] => 16509370 [patent_doc_number] => 20200388626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A SILICON-GERMANIUM SOURCE CONTACT LAYER AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/001270 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 51628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001270 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001270
Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same Aug 23, 2020 Issued
Array ( [id] => 16896262 [patent_doc_number] => 11037824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/999997 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999997
Semiconductor device and method for manufacturing the same Aug 20, 2020 Issued
Array ( [id] => 17137738 [patent_doc_number] => 11139305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-05 [patent_title] => Recessed access device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/993250 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 6092 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993250 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/993250
Recessed access device and manufacturing method thereof Aug 12, 2020 Issued
Array ( [id] => 17417260 [patent_doc_number] => 20220052164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => TRANSISTOR DEVICE WITH BURIED FIELD ELECTRODE CONNECTION [patent_app_type] => utility [patent_app_number] => 16/991478 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991478 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/991478
Transistor device with buried field electrode connection Aug 11, 2020 Issued
Array ( [id] => 17493631 [patent_doc_number] => 11282949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Semiconductor device and semiconductor circuit [patent_app_type] => utility [patent_app_number] => 16/989101 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17584 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 552 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989101 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989101
Semiconductor device and semiconductor circuit Aug 9, 2020 Issued
Array ( [id] => 17402874 [patent_doc_number] => 20220044965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => Conductive Via Of Integrated Circuitry, Memory Array Comprising Strings Of Memory Cells, Method Of Forming A Conductive Via Of Integrated Circuitry, And Method Of Forming A Memory Array Comprising Strings Of Memory Cells [patent_app_type] => utility [patent_app_number] => 16/987991 [patent_app_country] => US [patent_app_date] => 2020-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16987991 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/987991
Conductive via of integrated circuitry, memory array comprising strings of memory cells, method of forming a conductive via of integrated circuitry, and method of forming a memory array comprising strings of memory cells Aug 6, 2020 Issued
Array ( [id] => 16456043 [patent_doc_number] => 20200365469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => HYBRID GATE STACK INTEGRATION FOR STACKED VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/983587 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983587
Hybrid gate stack integration for stacked vertical transport field-effect transistors Aug 2, 2020 Issued
Array ( [id] => 16455981 [patent_doc_number] => 20200365407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/984033 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984033
Semiconductor device and manufacturing method thereof Aug 2, 2020 Issued
Array ( [id] => 17365976 [patent_doc_number] => 11233007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Staircase structure in three-dimensional memory device and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/944857 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 13490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16944857 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/944857
Staircase structure in three-dimensional memory device and method for forming the same Jul 30, 2020 Issued
Array ( [id] => 17544189 [patent_doc_number] => 11309323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Three-dimensional memory devices with drain select gate cut and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/944869 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 18003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16944869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/944869
Three-dimensional memory devices with drain select gate cut and methods for forming the same Jul 30, 2020 Issued
Array ( [id] => 17878580 [patent_doc_number] => 11450604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Staircase structure in three-dimensional memory device and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/944835 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 12451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16944835 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/944835
Staircase structure in three-dimensional memory device and method for forming the same Jul 30, 2020 Issued
Array ( [id] => 16731105 [patent_doc_number] => 20210098253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE AND METHOD FOR FORMING [patent_app_type] => utility [patent_app_number] => 16/943198 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943198
Semiconductor-on-insulator (SOI) substrate and method for forming Jul 29, 2020 Issued
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