Search

Hsien Ming Lee

Examiner (ID: 17169, Phone: (571)272-1863 , Office: P/2823 )

Most Active Art Unit
2823
Art Unit(s)
2814, 2823
Total Applications
2377
Issued Applications
2182
Pending Applications
27
Abandoned Applications
178

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14301037 [patent_doc_number] => 10290650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => Self-aligned tubular electrode portions inside memory openings for drain select gate electrodes in a three-dimensional memory device [patent_app_type] => utility [patent_app_number] => 15/888714 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 50 [patent_no_of_words] => 17534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888714 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/888714
Self-aligned tubular electrode portions inside memory openings for drain select gate electrodes in a three-dimensional memory device Feb 4, 2018 Issued
Array ( [id] => 13257257 [patent_doc_number] => 10141326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-27 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/885328 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885328 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885328
Semiconductor memory device Jan 30, 2018 Issued
Array ( [id] => 13283303 [patent_doc_number] => 10153242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Electronic device interconnections for high temperature operability [patent_app_type] => utility [patent_app_number] => 15/882680 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6858 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882680 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882680
Electronic device interconnections for high temperature operability Jan 28, 2018 Issued
Array ( [id] => 14429969 [patent_doc_number] => 10319798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Light emitting display apparatus [patent_app_type] => utility [patent_app_number] => 15/878825 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5628 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/878825
Light emitting display apparatus Jan 23, 2018 Issued
Array ( [id] => 13229113 [patent_doc_number] => 10128339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Superlattice materials and applications [patent_app_type] => utility [patent_app_number] => 15/878317 [patent_app_country] => US [patent_app_date] => 2018-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 105 [patent_no_of_words] => 46134 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878317 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/878317
Superlattice materials and applications Jan 22, 2018 Issued
Array ( [id] => 15752489 [patent_doc_number] => 10618334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => High speed and high power laser scribing methods and systems [patent_app_type] => utility [patent_app_number] => 15/877963 [patent_app_country] => US [patent_app_date] => 2018-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4718 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/877963
High speed and high power laser scribing methods and systems Jan 22, 2018 Issued
Array ( [id] => 14542751 [patent_doc_number] => 20190206997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => HIGH-VOLTAGE DRAIN EXTENDED MOS TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/876989 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876989 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876989
High-voltage drain extended MOS transistor Jan 21, 2018 Issued
Array ( [id] => 14616813 [patent_doc_number] => 10361113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Formation and in-situ treatment processes for gap fill layers [patent_app_type] => utility [patent_app_number] => 15/876583 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 10600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876583 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876583
Formation and in-situ treatment processes for gap fill layers Jan 21, 2018 Issued
Array ( [id] => 14094277 [patent_doc_number] => 10243053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-26 [patent_title] => Gate contact structure positioned above an active region of a transistor device [patent_app_type] => utility [patent_app_number] => 15/876316 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 41 [patent_no_of_words] => 7844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876316
Gate contact structure positioned above an active region of a transistor device Jan 21, 2018 Issued
Array ( [id] => 12800509 [patent_doc_number] => 20180158672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => Crystalline Semiconductor Growth on Amorphous and Poly-Crystalline Substrates [patent_app_type] => utility [patent_app_number] => 15/876048 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876048 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876048
Crystalline Semiconductor Growth on Amorphous and Poly-Crystalline Substrates Jan 18, 2018 Abandoned
15/875459 HETEROLITHIC MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON HIGHLY DOPED INTRINSIC SEMICONDUCTOR Jan 18, 2018 Abandoned
Array ( [id] => 14631489 [patent_doc_number] => 20190229114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => HETEROLITHIC MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON INTRINSIC SEMICONDUCTOR [patent_app_type] => utility [patent_app_number] => 15/875406 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875406 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/875406
Heterolithic microwave integrated circuits including gallium-nitride devices on intrinsic semiconductor Jan 18, 2018 Issued
Array ( [id] => 13976953 [patent_doc_number] => 10217846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Vertical field effect transistor formation with critical dimension control [patent_app_type] => utility [patent_app_number] => 15/873156 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 11668 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873156 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873156
Vertical field effect transistor formation with critical dimension control Jan 16, 2018 Issued
Array ( [id] => 14267843 [patent_doc_number] => 10283493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-07 [patent_title] => Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof [patent_app_type] => utility [patent_app_number] => 15/873101 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 53 [patent_no_of_words] => 26127 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873101 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873101
Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof Jan 16, 2018 Issued
Array ( [id] => 14367235 [patent_doc_number] => 10304932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Semiconductor device having a fin structure and a manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/871374 [patent_app_country] => US [patent_app_date] => 2018-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 8133 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871374 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/871374
Semiconductor device having a fin structure and a manufacturing method thereof Jan 14, 2018 Issued
Array ( [id] => 13832643 [patent_doc_number] => 20190019806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/870038 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870038 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/870038
Semiconductor device and method of manufacturing the same Jan 11, 2018 Issued
Array ( [id] => 13629871 [patent_doc_number] => 20180366488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/865669 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865669 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865669
Semiconductor device and manufacturing method thereof Jan 8, 2018 Issued
Array ( [id] => 15641107 [patent_doc_number] => 10593558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Method of manufacturing solar cell [patent_app_type] => utility [patent_app_number] => 15/866052 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5649 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866052 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/866052
Method of manufacturing solar cell Jan 8, 2018 Issued
Array ( [id] => 13976587 [patent_doc_number] => 10217658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Method and structure for minimizing fin reveal variation in FinFET transistor [patent_app_type] => utility [patent_app_number] => 15/864248 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4654 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864248 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/864248
Method and structure for minimizing fin reveal variation in FinFET transistor Jan 7, 2018 Issued
Array ( [id] => 17152672 [patent_doc_number] => 11145763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Vertical switching device with self-aligned contact [patent_app_type] => utility [patent_app_number] => 16/649171 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 12399 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649171
Vertical switching device with self-aligned contact Jan 3, 2018 Issued
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