
Hsien Ming Lee
Examiner (ID: 17169, Phone: (571)272-1863 , Office: P/2823 )
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2814, 2823 |
| Total Applications | 2377 |
| Issued Applications | 2182 |
| Pending Applications | 27 |
| Abandoned Applications | 178 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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Array
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 17/691641 | Substrate processing apparatus, elevator and method of manufacturing semiconductor device | Mar 9, 2022 | Issued |