
Hua Jasmine Song
Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )
| Most Active Art Unit | 2133 |
| Art Unit(s) | 2131, 2189, 2187, 2138, 2133, 2188 |
| Total Applications | 1393 |
| Issued Applications | 1256 |
| Pending Applications | 72 |
| Abandoned Applications | 80 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4101481
[patent_doc_number] => 06100131
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Method of fabricating a random access memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/873100
[patent_app_country] => US
[patent_app_date] => 1997-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4111
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/100/06100131.pdf
[firstpage_image] =>[orig_patent_app_number] => 873100
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/873100 | Method of fabricating a random access memory cell | Jun 10, 1997 | Issued |
Array
(
[id] => 4006634
[patent_doc_number] => 05888861
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow'
[patent_app_type] => 1
[patent_app_number] => 8/870474
[patent_app_country] => US
[patent_app_date] => 1997-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 4761
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/888/05888861.pdf
[firstpage_image] =>[orig_patent_app_number] => 870474
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/870474 | Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow | Jun 5, 1997 | Issued |
Array
(
[id] => 1335975
[patent_doc_number] => 06593178
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'BI-CMOS integrated circuit'
[patent_app_type] => B1
[patent_app_number] => 08/866968
[patent_app_country] => US
[patent_app_date] => 1997-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 48
[patent_no_of_words] => 4941
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/593/06593178.pdf
[firstpage_image] =>[orig_patent_app_number] => 08866968
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/866968 | BI-CMOS integrated circuit | Jun 1, 1997 | Issued |
Array
(
[id] => 3768877
[patent_doc_number] => 05849623
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'Method of forming thin film resistors on organic surfaces'
[patent_app_type] => 1
[patent_app_number] => 8/862672
[patent_app_country] => US
[patent_app_date] => 1997-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3746
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/849/05849623.pdf
[firstpage_image] =>[orig_patent_app_number] => 862672
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/862672 | Method of forming thin film resistors on organic surfaces | May 22, 1997 | Issued |
Array
(
[id] => 3881690
[patent_doc_number] => 05798287
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Method for forming a power MOS device chip'
[patent_app_type] => 1
[patent_app_number] => 8/861496
[patent_app_country] => US
[patent_app_date] => 1997-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1810
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/798/05798287.pdf
[firstpage_image] =>[orig_patent_app_number] => 861496
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/861496 | Method for forming a power MOS device chip | May 21, 1997 | Issued |
Array
(
[id] => 4214167
[patent_doc_number] => 06110763
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'One mask, power semiconductor device fabrication process'
[patent_app_type] => 1
[patent_app_number] => 8/861562
[patent_app_country] => US
[patent_app_date] => 1997-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 6227
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/110/06110763.pdf
[firstpage_image] =>[orig_patent_app_number] => 861562
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/861562 | One mask, power semiconductor device fabrication process | May 21, 1997 | Issued |
Array
(
[id] => 4062861
[patent_doc_number] => 05866463
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Method of manufacturing a semiconductor apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/861052
[patent_app_country] => US
[patent_app_date] => 1997-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 51
[patent_figures_cnt] => 86
[patent_no_of_words] => 20799
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/866/05866463.pdf
[firstpage_image] =>[orig_patent_app_number] => 861052
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/861052 | Method of manufacturing a semiconductor apparatus | May 20, 1997 | Issued |
Array
(
[id] => 3813409
[patent_doc_number] => 05789288
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Process for the fabrication of semiconductor devices having various buried regions'
[patent_app_type] => 1
[patent_app_number] => 8/854584
[patent_app_country] => US
[patent_app_date] => 1997-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 3393
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 406
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/789/05789288.pdf
[firstpage_image] =>[orig_patent_app_number] => 854584
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/854584 | Process for the fabrication of semiconductor devices having various buried regions | May 11, 1997 | Issued |
Array
(
[id] => 4000854
[patent_doc_number] => 05858852
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Fabrication process of a stack type semiconductor capacitive element'
[patent_app_type] => 1
[patent_app_number] => 8/853744
[patent_app_country] => US
[patent_app_date] => 1997-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 21
[patent_no_of_words] => 7541
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/858/05858852.pdf
[firstpage_image] =>[orig_patent_app_number] => 853744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/853744 | Fabrication process of a stack type semiconductor capacitive element | May 8, 1997 | Issued |
Array
(
[id] => 4023815
[patent_doc_number] => 05882967
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-16
[patent_title] => 'Process for buried diode formation in CMOS'
[patent_app_type] => 1
[patent_app_number] => 8/852850
[patent_app_country] => US
[patent_app_date] => 1997-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 30
[patent_no_of_words] => 10110
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/882/05882967.pdf
[firstpage_image] =>[orig_patent_app_number] => 852850
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/852850 | Process for buried diode formation in CMOS | May 6, 1997 | Issued |
Array
(
[id] => 3824571
[patent_doc_number] => 05731236
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Process to integrate a self-aligned contact structure, with a capacitor structure'
[patent_app_type] => 1
[patent_app_number] => 8/851400
[patent_app_country] => US
[patent_app_date] => 1997-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3267
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 410
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/731/05731236.pdf
[firstpage_image] =>[orig_patent_app_number] => 851400
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/851400 | Process to integrate a self-aligned contact structure, with a capacitor structure | May 4, 1997 | Issued |
Array
(
[id] => 3957394
[patent_doc_number] => 05930635
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Complementary Si/SiGe heterojunction bipolar technology'
[patent_app_type] => 1
[patent_app_number] => 8/850610
[patent_app_country] => US
[patent_app_date] => 1997-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3387
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/930/05930635.pdf
[firstpage_image] =>[orig_patent_app_number] => 850610
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/850610 | Complementary Si/SiGe heterojunction bipolar technology | May 1, 1997 | Issued |
Array
(
[id] => 4069604
[patent_doc_number] => 05933720
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'Method for manufacturing BiMOS device with improvement of high frequency characteristics of bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 8/840722
[patent_app_country] => US
[patent_app_date] => 1997-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 38
[patent_no_of_words] => 5820
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/933/05933720.pdf
[firstpage_image] =>[orig_patent_app_number] => 840722
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840722 | Method for manufacturing BiMOS device with improvement of high frequency characteristics of bipolar transistor | Apr 24, 1997 | Issued |
Array
(
[id] => 3966860
[patent_doc_number] => 05956578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Method of fabricating vertical FET with Schottky diode'
[patent_app_type] => 1
[patent_app_number] => 8/839226
[patent_app_country] => US
[patent_app_date] => 1997-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2409
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/956/05956578.pdf
[firstpage_image] =>[orig_patent_app_number] => 839226
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/839226 | Method of fabricating vertical FET with Schottky diode | Apr 22, 1997 | Issued |
Array
(
[id] => 3739430
[patent_doc_number] => 05753558
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Method of forming a capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/844384
[patent_app_country] => US
[patent_app_date] => 1997-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2498
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/753/05753558.pdf
[firstpage_image] =>[orig_patent_app_number] => 844384
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/844384 | Method of forming a capacitor | Apr 17, 1997 | Issued |
Array
(
[id] => 4001094
[patent_doc_number] => 05858868
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Method of manufacturing a laminated wiring structure preventing impurity diffusion therein from N+ and P+ regions in CMOS device with ohmic contact'
[patent_app_type] => 1
[patent_app_number] => 8/631036
[patent_app_country] => US
[patent_app_date] => 1997-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3504
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/858/05858868.pdf
[firstpage_image] =>[orig_patent_app_number] => 631036
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/631036 | Method of manufacturing a laminated wiring structure preventing impurity diffusion therein from N+ and P+ regions in CMOS device with ohmic contact | Apr 14, 1997 | Issued |
Array
(
[id] => 4038996
[patent_doc_number] => 05926716
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Method for forming a structure'
[patent_app_type] => 1
[patent_app_number] => 8/829255
[patent_app_country] => US
[patent_app_date] => 1997-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 3243
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926716.pdf
[firstpage_image] =>[orig_patent_app_number] => 829255
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/829255 | Method for forming a structure | Mar 30, 1997 | Issued |
Array
(
[id] => 4011942
[patent_doc_number] => 05879972
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'SRAM device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/809800
[patent_app_country] => US
[patent_app_date] => 1997-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 4228
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/879/05879972.pdf
[firstpage_image] =>[orig_patent_app_number] => 809800
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/809800 | SRAM device and method of manufacturing the same | Mar 26, 1997 | Issued |
Array
(
[id] => 3781972
[patent_doc_number] => 05821149
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Method of fabricating a heterobipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 8/815010
[patent_app_country] => US
[patent_app_date] => 1997-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2476
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/821/05821149.pdf
[firstpage_image] =>[orig_patent_app_number] => 815010
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/815010 | Method of fabricating a heterobipolar transistor | Mar 13, 1997 | Issued |
Array
(
[id] => 3875008
[patent_doc_number] => 05747353
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Method of making surface micro-machined accelerometer using silicon-on-insulator technology'
[patent_app_type] => 1
[patent_app_number] => 8/814352
[patent_app_country] => US
[patent_app_date] => 1997-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 4939
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/747/05747353.pdf
[firstpage_image] =>[orig_patent_app_number] => 814352
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/814352 | Method of making surface micro-machined accelerometer using silicon-on-insulator technology | Mar 10, 1997 | Issued |