Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3937031 [patent_doc_number] => 05915187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Method of manufacturing a semiconductor device with a pn junction provided through epitaxy' [patent_app_type] => 1 [patent_app_number] => 8/768482 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3307 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915187.pdf [firstpage_image] =>[orig_patent_app_number] => 768482 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768482
Method of manufacturing a semiconductor device with a pn junction provided through epitaxy Dec 17, 1996 Issued
Array ( [id] => 3875057 [patent_doc_number] => 05747356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Method for manufacturing ISRC MOSFET' [patent_app_type] => 1 [patent_app_number] => 8/760490 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 2011 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/747/05747356.pdf [firstpage_image] =>[orig_patent_app_number] => 760490 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760490
Method for manufacturing ISRC MOSFET Dec 4, 1996 Issued
Array ( [id] => 3881572 [patent_doc_number] => 05798280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Process for doping hemispherical grain silicon' [patent_app_type] => 1 [patent_app_number] => 8/753828 [patent_app_country] => US [patent_app_date] => 1996-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2255 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798280.pdf [firstpage_image] =>[orig_patent_app_number] => 753828 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753828
Process for doping hemispherical grain silicon Dec 1, 1996 Issued
Array ( [id] => 3807977 [patent_doc_number] => 05811332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method of fabricating a capacitor structure for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/757676 [patent_app_country] => US [patent_app_date] => 1996-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 8203 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811332.pdf [firstpage_image] =>[orig_patent_app_number] => 757676 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757676
Method of fabricating a capacitor structure for a semiconductor memory device Nov 28, 1996 Issued
08/758256 SUPER SELF-ALIGNED BIPOLAR TRANSISTOR AND METHOD FOR FABRICATING THEREOF Nov 26, 1996 Abandoned
Array ( [id] => 3791921 [patent_doc_number] => 05780364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Method to cure mobile ion contamination in semiconductor processing' [patent_app_type] => 1 [patent_app_number] => 8/759152 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1887 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780364.pdf [firstpage_image] =>[orig_patent_app_number] => 759152 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759152
Method to cure mobile ion contamination in semiconductor processing Nov 26, 1996 Issued
Array ( [id] => 3875312 [patent_doc_number] => 05747374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Methods of fabricating bipolar transistors having separately formed intrinsic base and link-up regions' [patent_app_type] => 1 [patent_app_number] => 8/757802 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4276 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/747/05747374.pdf [firstpage_image] =>[orig_patent_app_number] => 757802 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757802
Methods of fabricating bipolar transistors having separately formed intrinsic base and link-up regions Nov 26, 1996 Issued
Array ( [id] => 3849269 [patent_doc_number] => 05766993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Method of fabricating storage node electrode, for DRAM devices, using polymer spacers, to obtain polysilicon columns, with minimum spacing between columns' [patent_app_type] => 1 [patent_app_number] => 8/756086 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3037 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 567 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/766/05766993.pdf [firstpage_image] =>[orig_patent_app_number] => 756086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756086
Method of fabricating storage node electrode, for DRAM devices, using polymer spacers, to obtain polysilicon columns, with minimum spacing between columns Nov 24, 1996 Issued
Array ( [id] => 3812530 [patent_doc_number] => 05710072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells' [patent_app_type] => 1 [patent_app_number] => 8/737236 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5147 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710072.pdf [firstpage_image] =>[orig_patent_app_number] => 737236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/737236
Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells Nov 17, 1996 Issued
Array ( [id] => 3832363 [patent_doc_number] => 05814549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Method of making porous-si capacitor dram cell' [patent_app_type] => 1 [patent_app_number] => 8/746858 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2773 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814549.pdf [firstpage_image] =>[orig_patent_app_number] => 746858 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746858
Method of making porous-si capacitor dram cell Nov 17, 1996 Issued
Array ( [id] => 4190943 [patent_doc_number] => 06130106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Method for limiting emission current in field emission devices' [patent_app_type] => 1 [patent_app_number] => 8/748816 [patent_app_country] => US [patent_app_date] => 1996-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1887 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130106.pdf [firstpage_image] =>[orig_patent_app_number] => 748816 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748816
Method for limiting emission current in field emission devices Nov 13, 1996 Issued
Array ( [id] => 3969101 [patent_doc_number] => 05904535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Method of fabricating a bipolar integrated structure' [patent_app_type] => 1 [patent_app_number] => 8/748969 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2295 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904535.pdf [firstpage_image] =>[orig_patent_app_number] => 748969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748969
Method of fabricating a bipolar integrated structure Nov 12, 1996 Issued
Array ( [id] => 3647166 [patent_doc_number] => 05683931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Method of forming a capacitor over a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/748636 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3427 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/683/05683931.pdf [firstpage_image] =>[orig_patent_app_number] => 748636 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748636
Method of forming a capacitor over a semiconductor substrate Nov 12, 1996 Issued
Array ( [id] => 3791304 [patent_doc_number] => 05780323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug' [patent_app_type] => 1 [patent_app_number] => 8/758281 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6264 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780323.pdf [firstpage_image] =>[orig_patent_app_number] => 758281 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758281
Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug Nov 11, 1996 Issued
Array ( [id] => 4090135 [patent_doc_number] => RE036644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Tapered via, structures made therewith, and methods of producing same' [patent_app_type] => 2 [patent_app_number] => 8/745757 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8348 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036644.pdf [firstpage_image] =>[orig_patent_app_number] => 745757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/745757
Tapered via, structures made therewith, and methods of producing same Nov 7, 1996 Issued
Array ( [id] => 3808206 [patent_doc_number] => 05811349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method for growing a semiconductor layer' [patent_app_type] => 1 [patent_app_number] => 8/743530 [patent_app_country] => US [patent_app_date] => 1996-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 7707 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811349.pdf [firstpage_image] =>[orig_patent_app_number] => 743530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/743530
Method for growing a semiconductor layer Nov 3, 1996 Issued
Array ( [id] => 3841458 [patent_doc_number] => 05707900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Method of heat-treating semiconductor crystal of a group II-group VI compound' [patent_app_type] => 1 [patent_app_number] => 8/743408 [patent_app_country] => US [patent_app_date] => 1996-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1563 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/707/05707900.pdf [firstpage_image] =>[orig_patent_app_number] => 743408 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/743408
Method of heat-treating semiconductor crystal of a group II-group VI compound Oct 31, 1996 Issued
Array ( [id] => 3813621 [patent_doc_number] => 05789304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method of forming a capacitor' [patent_app_type] => 1 [patent_app_number] => 8/741832 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1858 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789304.pdf [firstpage_image] =>[orig_patent_app_number] => 741832 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/741832
Method of forming a capacitor Oct 30, 1996 Issued
Array ( [id] => 3744896 [patent_doc_number] => 05716859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Method of fabricating a silicon BJT' [patent_app_type] => 1 [patent_app_number] => 8/741444 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4364 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/716/05716859.pdf [firstpage_image] =>[orig_patent_app_number] => 741444 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/741444
Method of fabricating a silicon BJT Oct 30, 1996 Issued
Array ( [id] => 3828211 [patent_doc_number] => 05739060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method of fabricating a capacitor structure for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/735560 [patent_app_country] => US [patent_app_date] => 1996-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 43 [patent_no_of_words] => 10132 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739060.pdf [firstpage_image] =>[orig_patent_app_number] => 735560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735560
Method of fabricating a capacitor structure for a semiconductor memory device Oct 22, 1996 Issued
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