Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3725327 [patent_doc_number] => 05700711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Method of manufacturing an SRAM load shield' [patent_app_type] => 1 [patent_app_number] => 8/735222 [patent_app_country] => US [patent_app_date] => 1996-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3392 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/700/05700711.pdf [firstpage_image] =>[orig_patent_app_number] => 735222 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735222
Method of manufacturing an SRAM load shield Oct 21, 1996 Issued
Array ( [id] => 3943161 [patent_doc_number] => 05976906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method for manufacturing a solid state image sensing device' [patent_app_type] => 1 [patent_app_number] => 8/733914 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 6233 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976906.pdf [firstpage_image] =>[orig_patent_app_number] => 733914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733914
Method for manufacturing a solid state image sensing device Oct 17, 1996 Issued
Array ( [id] => 4037890 [patent_doc_number] => RE036475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of forming a via plug in a semiconductor device' [patent_app_type] => 2 [patent_app_number] => 8/734784 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1169 [patent_no_of_claims] => 159 [patent_no_of_ind_claims] => 145 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036475.pdf [firstpage_image] =>[orig_patent_app_number] => 734784 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/734784
Method of forming a via plug in a semiconductor device Oct 14, 1996 Issued
Array ( [id] => 4221850 [patent_doc_number] => 06010917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Electrically isolated interconnects and conductive layers in semiconductor device manufacturing' [patent_app_type] => 1 [patent_app_number] => 8/725646 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4561 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010917.pdf [firstpage_image] =>[orig_patent_app_number] => 725646 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/725646
Electrically isolated interconnects and conductive layers in semiconductor device manufacturing Oct 14, 1996 Issued
Array ( [id] => 3686613 [patent_doc_number] => 05696007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Method for manufacturing a super self-aligned bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/729840 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4762 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696007.pdf [firstpage_image] =>[orig_patent_app_number] => 729840 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/729840
Method for manufacturing a super self-aligned bipolar transistor Oct 14, 1996 Issued
Array ( [id] => 3723439 [patent_doc_number] => 05681764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Method for forming a bipolar integrated ink jet printhead driver' [patent_app_type] => 1 [patent_app_number] => 8/729066 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5015 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/681/05681764.pdf [firstpage_image] =>[orig_patent_app_number] => 729066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/729066
Method for forming a bipolar integrated ink jet printhead driver Oct 9, 1996 Issued
Array ( [id] => 3730781 [patent_doc_number] => 05665616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Process of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/731012 [patent_app_country] => US [patent_app_date] => 1996-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 5517 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665616.pdf [firstpage_image] =>[orig_patent_app_number] => 731012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731012
Process of manufacturing a semiconductor device Oct 8, 1996 Issued
Array ( [id] => 4056833 [patent_doc_number] => 05863818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Multilevel transistor fabrication method having an inverted, upper level transistor' [patent_app_type] => 1 [patent_app_number] => 8/727050 [patent_app_country] => US [patent_app_date] => 1996-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4140 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/863/05863818.pdf [firstpage_image] =>[orig_patent_app_number] => 727050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727050
Multilevel transistor fabrication method having an inverted, upper level transistor Oct 7, 1996 Issued
Array ( [id] => 1368341 [patent_doc_number] => RE038049 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemical mechanical polishing' [patent_app_type] => E1 [patent_app_number] => 08/759058 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2734 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038049.pdf [firstpage_image] =>[orig_patent_app_number] => 08759058 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759058
Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemical mechanical polishing Oct 6, 1996 Issued
Array ( [id] => 3687283 [patent_doc_number] => 05691214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Method of manufacturing semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/725760 [patent_app_country] => US [patent_app_date] => 1996-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4553 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691214.pdf [firstpage_image] =>[orig_patent_app_number] => 725760 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/725760
Method of manufacturing semiconductor devices Oct 3, 1996 Issued
Array ( [id] => 4012356 [patent_doc_number] => 05879999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method of manufacturing an insulated gate semiconductor device having a spacer extension' [patent_app_type] => 1 [patent_app_number] => 8/720510 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3217 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/879/05879999.pdf [firstpage_image] =>[orig_patent_app_number] => 720510 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/720510
Method of manufacturing an insulated gate semiconductor device having a spacer extension Sep 29, 1996 Issued
Array ( [id] => 3656621 [patent_doc_number] => 05658821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Method of improving uniformity of metal-to-poly capacitors composed by polysilicon oxide and avoiding device damage' [patent_app_type] => 1 [patent_app_number] => 8/721668 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1911 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/658/05658821.pdf [firstpage_image] =>[orig_patent_app_number] => 721668 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721668
Method of improving uniformity of metal-to-poly capacitors composed by polysilicon oxide and avoiding device damage Sep 26, 1996 Issued
Array ( [id] => 3937867 [patent_doc_number] => 05872019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Method for fabricating a field emitter array incorporated with metal oxide semiconductor field effect transistors' [patent_app_type] => 1 [patent_app_number] => 8/718789 [patent_app_country] => US [patent_app_date] => 1996-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 38 [patent_no_of_words] => 4098 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872019.pdf [firstpage_image] =>[orig_patent_app_number] => 718789 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/718789
Method for fabricating a field emitter array incorporated with metal oxide semiconductor field effect transistors Sep 23, 1996 Issued
Array ( [id] => 3896523 [patent_doc_number] => 05897357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method of forming a field effect transistor and method of forming CMOS integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 8/717014 [patent_app_country] => US [patent_app_date] => 1996-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2939 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897357.pdf [firstpage_image] =>[orig_patent_app_number] => 717014 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/717014
Method of forming a field effect transistor and method of forming CMOS integrated circuitry Sep 19, 1996 Issued
Array ( [id] => 3727130 [patent_doc_number] => 05702990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells' [patent_app_type] => 1 [patent_app_number] => 8/712616 [patent_app_country] => US [patent_app_date] => 1996-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2193 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702990.pdf [firstpage_image] =>[orig_patent_app_number] => 712616 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/712616
Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells Sep 12, 1996 Issued
Array ( [id] => 4038662 [patent_doc_number] => 05926692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method of manufacturing a support structure for a semiconductor pressure transducer' [patent_app_type] => 1 [patent_app_number] => 8/713266 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3908 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926692.pdf [firstpage_image] =>[orig_patent_app_number] => 713266 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713266
Method of manufacturing a support structure for a semiconductor pressure transducer Sep 11, 1996 Issued
Array ( [id] => 3841261 [patent_doc_number] => 05707886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Process for providing electrostatic discharge protection to an integrated circuit output pad' [patent_app_type] => 1 [patent_app_number] => 8/712896 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5065 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/707/05707886.pdf [firstpage_image] =>[orig_patent_app_number] => 712896 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/712896
Process for providing electrostatic discharge protection to an integrated circuit output pad Sep 11, 1996 Issued
Array ( [id] => 4002952 [patent_doc_number] => 06004860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'SOI substrate and a method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/705956 [patent_app_country] => US [patent_app_date] => 1996-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 2015 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004860.pdf [firstpage_image] =>[orig_patent_app_number] => 705956 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705956
SOI substrate and a method for fabricating the same Aug 29, 1996 Issued
Array ( [id] => 3999229 [patent_doc_number] => 05950068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method of fabricating semiconductor devices having a mesa structure for improved surface voltage breakdown characteristics' [patent_app_type] => 1 [patent_app_number] => 8/705616 [patent_app_country] => US [patent_app_date] => 1996-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 7222 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950068.pdf [firstpage_image] =>[orig_patent_app_number] => 705616 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705616
Method of fabricating semiconductor devices having a mesa structure for improved surface voltage breakdown characteristics Aug 29, 1996 Issued
Array ( [id] => 3965044 [patent_doc_number] => 05885884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Process for fabricating a microcrystalline silicon structure' [patent_app_type] => 1 [patent_app_number] => 8/703906 [patent_app_country] => US [patent_app_date] => 1996-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5387 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/885/05885884.pdf [firstpage_image] =>[orig_patent_app_number] => 703906 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703906
Process for fabricating a microcrystalline silicon structure Aug 26, 1996 Issued
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