Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3738939 [patent_doc_number] => 05753524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Method of forming a plateau and a cover on the plateau in particular on a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/668628 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1515 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/753/05753524.pdf [firstpage_image] =>[orig_patent_app_number] => 668628 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668628
Method of forming a plateau and a cover on the plateau in particular on a semiconductor substrate Jun 18, 1996 Issued
Array ( [id] => 3757056 [patent_doc_number] => 05721154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Method for fabricating a four fin capacitor structure' [patent_app_type] => 1 [patent_app_number] => 8/665602 [patent_app_country] => US [patent_app_date] => 1996-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3095 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721154.pdf [firstpage_image] =>[orig_patent_app_number] => 665602 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665602
Method for fabricating a four fin capacitor structure Jun 17, 1996 Issued
Array ( [id] => 3660970 [patent_doc_number] => 05624856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Method for forming a lateral bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/662964 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3022 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/624/05624856.pdf [firstpage_image] =>[orig_patent_app_number] => 662964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662964
Method for forming a lateral bipolar transistor Jun 12, 1996 Issued
Array ( [id] => 3804628 [patent_doc_number] => 05830795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Simplified masking process for programmable logic device manufacture' [patent_app_type] => 1 [patent_app_number] => 8/664190 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3457 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/830/05830795.pdf [firstpage_image] =>[orig_patent_app_number] => 664190 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664190
Simplified masking process for programmable logic device manufacture Jun 9, 1996 Issued
08/659868 BIPOLAR ALIGNMENT MARK FOR SEMICONDUCTOR DEVICE AND PROCESS FOR FORMING THE SAME Jun 6, 1996 Abandoned
Array ( [id] => 3739144 [patent_doc_number] => 05753539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Method of making an integrated circuit with windowed fuse element and contact pad' [patent_app_type] => 1 [patent_app_number] => 8/658571 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2354 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/753/05753539.pdf [firstpage_image] =>[orig_patent_app_number] => 658571 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658571
Method of making an integrated circuit with windowed fuse element and contact pad Jun 4, 1996 Issued
Array ( [id] => 3760537 [patent_doc_number] => 05851913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process' [patent_app_type] => 1 [patent_app_number] => 8/655246 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 3651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851913.pdf [firstpage_image] =>[orig_patent_app_number] => 655246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655246
Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process Jun 4, 1996 Issued
Array ( [id] => 3884158 [patent_doc_number] => 05776789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Method for fabricating a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/660324 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 72 [patent_no_of_words] => 14690 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/776/05776789.pdf [firstpage_image] =>[orig_patent_app_number] => 660324 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660324
Method for fabricating a semiconductor memory device Jun 3, 1996 Issued
Array ( [id] => 3806118 [patent_doc_number] => 05854108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Method and system for providing a double diffuse implant junction in a flash device' [patent_app_type] => 1 [patent_app_number] => 8/658038 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3027 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854108.pdf [firstpage_image] =>[orig_patent_app_number] => 658038 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658038
Method and system for providing a double diffuse implant junction in a flash device Jun 3, 1996 Issued
Array ( [id] => 3858858 [patent_doc_number] => 05792699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for reduction of reverse short channel effect in MOSFET' [patent_app_type] => 1 [patent_app_number] => 8/657074 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3167 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792699.pdf [firstpage_image] =>[orig_patent_app_number] => 657074 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657074
Method for reduction of reverse short channel effect in MOSFET Jun 2, 1996 Issued
Array ( [id] => 3860875 [patent_doc_number] => 05795813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Radiation-hardening of SOI by ion implantation into the buried oxide layer' [patent_app_type] => 1 [patent_app_number] => 8/655780 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1591 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/795/05795813.pdf [firstpage_image] =>[orig_patent_app_number] => 655780 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655780
Radiation-hardening of SOI by ion implantation into the buried oxide layer May 30, 1996 Issued
Array ( [id] => 4182649 [patent_doc_number] => 06150252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Multi-stage semiconductor cavity filling process' [patent_app_type] => 1 [patent_app_number] => 8/654810 [patent_app_country] => US [patent_app_date] => 1996-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5442 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150252.pdf [firstpage_image] =>[orig_patent_app_number] => 654810 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/654810
Multi-stage semiconductor cavity filling process May 28, 1996 Issued
08/657060 BIPOLAR SILICON-ON-INSULATOR STRUCTURE May 27, 1996 Abandoned
90/004250 METHOD OF MAKING CMOS INTEGRATED CIRCUIT DEVICE May 27, 1996 Issued
Array ( [id] => 3858790 [patent_doc_number] => 05792694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for fabricating a semiconductor memory cell structure' [patent_app_type] => 1 [patent_app_number] => 8/648688 [patent_app_country] => US [patent_app_date] => 1996-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 2511 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792694.pdf [firstpage_image] =>[orig_patent_app_number] => 648688 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/648688
Method for fabricating a semiconductor memory cell structure May 15, 1996 Issued
Array ( [id] => 3730811 [patent_doc_number] => 05665619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method of fabricating a self-aligned contact trench DMOS transistor structure' [patent_app_type] => 1 [patent_app_number] => 8/645446 [patent_app_country] => US [patent_app_date] => 1996-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 19 [patent_no_of_words] => 1946 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665619.pdf [firstpage_image] =>[orig_patent_app_number] => 645446 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/645446
Method of fabricating a self-aligned contact trench DMOS transistor structure May 12, 1996 Issued
08/648526 METHOD OF FABRICATING VERY HIGH GAIN HETEROJUNCTION BIPOLAR TRANSISTORS May 12, 1996 Abandoned
Array ( [id] => 3660111 [patent_doc_number] => 05648281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/647073 [patent_app_country] => US [patent_app_date] => 1996-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 55 [patent_no_of_words] => 18013 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648281.pdf [firstpage_image] =>[orig_patent_app_number] => 647073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/647073
Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate May 7, 1996 Issued
Array ( [id] => 3620002 [patent_doc_number] => 05688712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Process for producing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/643938 [patent_app_country] => US [patent_app_date] => 1996-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 7489 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/688/05688712.pdf [firstpage_image] =>[orig_patent_app_number] => 643938 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/643938
Process for producing a semiconductor device May 6, 1996 Issued
Array ( [id] => 3685635 [patent_doc_number] => 05663085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Method for fabricating capacitive element of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/637036 [patent_app_country] => US [patent_app_date] => 1996-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 25 [patent_no_of_words] => 6722 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663085.pdf [firstpage_image] =>[orig_patent_app_number] => 637036 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/637036
Method for fabricating capacitive element of semiconductor memory device Apr 23, 1996 Issued
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