| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_doc_number] => 05753524
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[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Method of forming a plateau and a cover on the plateau in particular on a semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 8/668628
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[patent_app_date] => 1996-06-19
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Array
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[patent_doc_number] => 05721154
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[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Method for fabricating a four fin capacitor structure'
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[patent_app_number] => 8/665602
[patent_app_country] => US
[patent_app_date] => 1996-06-18
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[firstpage_image] =>[orig_patent_app_number] => 665602
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/665602 | Method for fabricating a four fin capacitor structure | Jun 17, 1996 | Issued |
Array
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[id] => 3660970
[patent_doc_number] => 05624856
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[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Method for forming a lateral bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 8/662964
[patent_app_country] => US
[patent_app_date] => 1996-06-13
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[firstpage_image] =>[orig_patent_app_number] => 662964
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/662964 | Method for forming a lateral bipolar transistor | Jun 12, 1996 | Issued |
Array
(
[id] => 3804628
[patent_doc_number] => 05830795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Simplified masking process for programmable logic device manufacture'
[patent_app_type] => 1
[patent_app_number] => 8/664190
[patent_app_country] => US
[patent_app_date] => 1996-06-10
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[firstpage_image] =>[orig_patent_app_number] => 664190
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/664190 | Simplified masking process for programmable logic device manufacture | Jun 9, 1996 | Issued |
| 08/659868 | BIPOLAR ALIGNMENT MARK FOR SEMICONDUCTOR DEVICE AND PROCESS FOR FORMING THE SAME | Jun 6, 1996 | Abandoned |
Array
(
[id] => 3739144
[patent_doc_number] => 05753539
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[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Method of making an integrated circuit with windowed fuse element and contact pad'
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Array
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[id] => 3760537
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[patent_issue_date] => 1998-12-22
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Array
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[id] => 3884158
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[patent_issue_date] => 1998-07-07
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[firstpage_image] =>[orig_patent_app_number] => 660324
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/660324 | Method for fabricating a semiconductor memory device | Jun 3, 1996 | Issued |
Array
(
[id] => 3806118
[patent_doc_number] => 05854108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-29
[patent_title] => 'Method and system for providing a double diffuse implant junction in a flash device'
[patent_app_type] => 1
[patent_app_number] => 8/658038
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[patent_app_date] => 1996-06-04
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[patent_drawing_sheets_cnt] => 6
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[firstpage_image] =>[orig_patent_app_number] => 658038
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/658038 | Method and system for providing a double diffuse implant junction in a flash device | Jun 3, 1996 | Issued |
Array
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[id] => 3858858
[patent_doc_number] => 05792699
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[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Method for reduction of reverse short channel effect in MOSFET'
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[patent_app_date] => 1996-06-03
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[firstpage_image] =>[orig_patent_app_number] => 657074
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/657074 | Method for reduction of reverse short channel effect in MOSFET | Jun 2, 1996 | Issued |
Array
(
[id] => 3860875
[patent_doc_number] => 05795813
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Radiation-hardening of SOI by ion implantation into the buried oxide layer'
[patent_app_type] => 1
[patent_app_number] => 8/655780
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/655780 | Radiation-hardening of SOI by ion implantation into the buried oxide layer | May 30, 1996 | Issued |
Array
(
[id] => 4182649
[patent_doc_number] => 06150252
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Multi-stage semiconductor cavity filling process'
[patent_app_type] => 1
[patent_app_number] => 8/654810
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 654810
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/654810 | Multi-stage semiconductor cavity filling process | May 28, 1996 | Issued |
| 08/657060 | BIPOLAR SILICON-ON-INSULATOR STRUCTURE | May 27, 1996 | Abandoned |
| 90/004250 | METHOD OF MAKING CMOS INTEGRATED CIRCUIT DEVICE | May 27, 1996 | Issued |
Array
(
[id] => 3858790
[patent_doc_number] => 05792694
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[patent_kind] => NA
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[patent_title] => 'Method for fabricating a semiconductor memory cell structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/648688 | Method for fabricating a semiconductor memory cell structure | May 15, 1996 | Issued |
Array
(
[id] => 3730811
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Method of fabricating a self-aligned contact trench DMOS transistor structure'
[patent_app_type] => 1
[patent_app_number] => 8/645446
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[patent_app_date] => 1996-05-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/645446 | Method of fabricating a self-aligned contact trench DMOS transistor structure | May 12, 1996 | Issued |
| 08/648526 | METHOD OF FABRICATING VERY HIGH GAIN HETEROJUNCTION BIPOLAR TRANSISTORS | May 12, 1996 | Abandoned |
Array
(
[id] => 3660111
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[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/647073 | Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate | May 7, 1996 | Issued |
Array
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Array
(
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[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Method for fabricating capacitive element of semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/637036 | Method for fabricating capacitive element of semiconductor memory device | Apr 23, 1996 | Issued |