Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3740465 [patent_doc_number] => 05786245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Method for forming a stable SRAM cell using low backgate biased threshold voltage select transistors' [patent_app_type] => 1 [patent_app_number] => 8/607414 [patent_app_country] => US [patent_app_date] => 1996-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4271 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786245.pdf [firstpage_image] =>[orig_patent_app_number] => 607414 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/607414
Method for forming a stable SRAM cell using low backgate biased threshold voltage select transistors Feb 27, 1996 Issued
Array ( [id] => 3876640 [patent_doc_number] => 05728595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Method of fabricating a self-aligned contact hole for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/605496 [patent_app_country] => US [patent_app_date] => 1996-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 9427 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/728/05728595.pdf [firstpage_image] =>[orig_patent_app_number] => 605496 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/605496
Method of fabricating a self-aligned contact hole for a semiconductor device Feb 25, 1996 Issued
Array ( [id] => 3791322 [patent_doc_number] => 05780324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Method of manufacturing a vertical semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/605637 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 39 [patent_no_of_words] => 11060 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780324.pdf [firstpage_image] =>[orig_patent_app_number] => 605637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/605637
Method of manufacturing a vertical semiconductor device Feb 21, 1996 Issued
Array ( [id] => 3740308 [patent_doc_number] => 05786233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Photo-assisted annealing process for activation of acceptors in semiconductor compound layers' [patent_app_type] => 1 [patent_app_number] => 8/603959 [patent_app_country] => US [patent_app_date] => 1996-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786233.pdf [firstpage_image] =>[orig_patent_app_number] => 603959 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/603959
Photo-assisted annealing process for activation of acceptors in semiconductor compound layers Feb 19, 1996 Issued
Array ( [id] => 3759511 [patent_doc_number] => 05843814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Method of forming BiCMOS circuitry' [patent_app_type] => 1 [patent_app_number] => 8/601966 [patent_app_country] => US [patent_app_date] => 1996-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3241 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843814.pdf [firstpage_image] =>[orig_patent_app_number] => 601966 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/601966
Method of forming BiCMOS circuitry Feb 14, 1996 Issued
Array ( [id] => 3884145 [patent_doc_number] => 05776788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Method for forming a strong dielectric film by the sol-gel technique and a method for manufacturing a capacitor' [patent_app_type] => 1 [patent_app_number] => 8/601884 [patent_app_country] => US [patent_app_date] => 1996-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 5585 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/776/05776788.pdf [firstpage_image] =>[orig_patent_app_number] => 601884 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/601884
Method for forming a strong dielectric film by the sol-gel technique and a method for manufacturing a capacitor Feb 14, 1996 Issued
Array ( [id] => 4050332 [patent_doc_number] => 05943564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'BiCMOS process for forming double-poly MOS and bipolar transistors with substantially identical device architectures' [patent_app_type] => 1 [patent_app_number] => 8/600632 [patent_app_country] => US [patent_app_date] => 1996-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 3742 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943564.pdf [firstpage_image] =>[orig_patent_app_number] => 600632 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/600632
BiCMOS process for forming double-poly MOS and bipolar transistors with substantially identical device architectures Feb 12, 1996 Issued
Array ( [id] => 3885051 [patent_doc_number] => 05723353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Process for manufacturing a sensor' [patent_app_type] => 1 [patent_app_number] => 8/599838 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5601 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/723/05723353.pdf [firstpage_image] =>[orig_patent_app_number] => 599838 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/599838
Process for manufacturing a sensor Feb 11, 1996 Issued
Array ( [id] => 3645707 [patent_doc_number] => 05637510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Method for fabricating solar cell' [patent_app_type] => 1 [patent_app_number] => 8/596414 [patent_app_country] => US [patent_app_date] => 1996-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 24 [patent_no_of_words] => 3753 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/637/05637510.pdf [firstpage_image] =>[orig_patent_app_number] => 596414 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/596414
Method for fabricating solar cell Feb 1, 1996 Issued
Array ( [id] => 3692985 [patent_doc_number] => 05679593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Method of fabricating a high resistance integrated circuit resistor' [patent_app_type] => 1 [patent_app_number] => 8/595232 [patent_app_country] => US [patent_app_date] => 1996-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2460 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/679/05679593.pdf [firstpage_image] =>[orig_patent_app_number] => 595232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/595232
Method of fabricating a high resistance integrated circuit resistor Jan 31, 1996 Issued
Array ( [id] => 3808192 [patent_doc_number] => 05811348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method for separating a device-forming layer from a base body' [patent_app_type] => 1 [patent_app_number] => 8/595382 [patent_app_country] => US [patent_app_date] => 1996-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6365 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811348.pdf [firstpage_image] =>[orig_patent_app_number] => 595382 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/595382
Method for separating a device-forming layer from a base body Jan 31, 1996 Issued
Array ( [id] => 3815382 [patent_doc_number] => 05770498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Process for forming a diffusion barrier using an insulating spacer layer' [patent_app_type] => 1 [patent_app_number] => 8/594794 [patent_app_country] => US [patent_app_date] => 1996-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3105 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770498.pdf [firstpage_image] =>[orig_patent_app_number] => 594794 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/594794
Process for forming a diffusion barrier using an insulating spacer layer Jan 30, 1996 Issued
Array ( [id] => 3759726 [patent_doc_number] => 05843828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Method for fabricating a semiconductor device with bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/593416 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 7736 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843828.pdf [firstpage_image] =>[orig_patent_app_number] => 593416 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/593416
Method for fabricating a semiconductor device with bipolar transistor Jan 28, 1996 Issued
Array ( [id] => 3869582 [patent_doc_number] => 05763287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method of fabricating semiconductor optical device' [patent_app_type] => 1 [patent_app_number] => 8/593348 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 8109 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/763/05763287.pdf [firstpage_image] =>[orig_patent_app_number] => 593348 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/593348
Method of fabricating semiconductor optical device Jan 28, 1996 Issued
Array ( [id] => 3656152 [patent_doc_number] => 05622889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'High capacitance capacitor manufacturing method' [patent_app_type] => 1 [patent_app_number] => 8/591391 [patent_app_country] => US [patent_app_date] => 1996-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2992 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622889.pdf [firstpage_image] =>[orig_patent_app_number] => 591391 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/591391
High capacitance capacitor manufacturing method Jan 24, 1996 Issued
Array ( [id] => 3730057 [patent_doc_number] => 05693557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/590086 [patent_app_country] => US [patent_app_date] => 1996-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 27 [patent_no_of_words] => 5502 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/693/05693557.pdf [firstpage_image] =>[orig_patent_app_number] => 590086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590086
Method of fabricating a semiconductor device Jan 23, 1996 Issued
Array ( [id] => 3657728 [patent_doc_number] => 05627096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Manufacturing method of electric charge transferring devices' [patent_app_type] => 1 [patent_app_number] => 8/590178 [patent_app_country] => US [patent_app_date] => 1996-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 25 [patent_no_of_words] => 5932 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627096.pdf [firstpage_image] =>[orig_patent_app_number] => 590178 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590178
Manufacturing method of electric charge transferring devices Jan 22, 1996 Issued
Array ( [id] => 3664644 [patent_doc_number] => 05597760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Process of fabricating semiconductor device having capacitor increased in capacitance by roughening surface of accumulating electrode' [patent_app_type] => 1 [patent_app_number] => 8/589268 [patent_app_country] => US [patent_app_date] => 1996-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 5888 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/597/05597760.pdf [firstpage_image] =>[orig_patent_app_number] => 589268 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/589268
Process of fabricating semiconductor device having capacitor increased in capacitance by roughening surface of accumulating electrode Jan 21, 1996 Issued
Array ( [id] => 3728125 [patent_doc_number] => 05652170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Method for etching sloped contact openings in polysilicon' [patent_app_type] => 1 [patent_app_number] => 8/589622 [patent_app_country] => US [patent_app_date] => 1996-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4094 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652170.pdf [firstpage_image] =>[orig_patent_app_number] => 589622 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/589622
Method for etching sloped contact openings in polysilicon Jan 21, 1996 Issued
Array ( [id] => 3660446 [patent_doc_number] => 05656533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Method of preventing polysilicon stringers during formation of a stacked double polysilicon structure by using dielectric sidewall spacers' [patent_app_type] => 1 [patent_app_number] => 8/587400 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 1895 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656533.pdf [firstpage_image] =>[orig_patent_app_number] => 587400 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/587400
Method of preventing polysilicon stringers during formation of a stacked double polysilicon structure by using dielectric sidewall spacers Jan 16, 1996 Issued
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