Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
08/562156 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Nov 21, 1995 Abandoned
Array ( [id] => 3849310 [patent_doc_number] => 05766996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/561020 [patent_app_country] => US [patent_app_date] => 1995-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 63 [patent_no_of_words] => 4982 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/766/05766996.pdf [firstpage_image] =>[orig_patent_app_number] => 561020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/561020
Method of manufacturing a semiconductor device Nov 20, 1995 Issued
Array ( [id] => 3726815 [patent_doc_number] => 05670396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Method of forming a DMOS-controlled lateral bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/561473 [patent_app_country] => US [patent_app_date] => 1995-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670396.pdf [firstpage_image] =>[orig_patent_app_number] => 561473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/561473
Method of forming a DMOS-controlled lateral bipolar transistor Nov 20, 1995 Issued
Array ( [id] => 3836364 [patent_doc_number] => 05846846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method for making a superconducting field-effect device with grain boundary channel' [patent_app_type] => 1 [patent_app_number] => 8/560962 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3552 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846846.pdf [firstpage_image] =>[orig_patent_app_number] => 560962 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560962
Method for making a superconducting field-effect device with grain boundary channel Nov 19, 1995 Issued
Array ( [id] => 3729852 [patent_doc_number] => 05693543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Method of manufacturing a semiconductor IIL device with dielectric and diffusion isolation' [patent_app_type] => 1 [patent_app_number] => 8/540372 [patent_app_country] => US [patent_app_date] => 1995-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 8187 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/693/05693543.pdf [firstpage_image] =>[orig_patent_app_number] => 540372 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540372
Method of manufacturing a semiconductor IIL device with dielectric and diffusion isolation Nov 16, 1995 Issued
08/560494 DEVICE AND METHOD FOR EPITAXIALLY GROWING GALLIUM NITRIDE LAYERS Nov 16, 1995 Abandoned
Array ( [id] => 3700371 [patent_doc_number] => 05646075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Method for optimizing thermal budgets in fabricating semiconductors' [patent_app_type] => 1 [patent_app_number] => 8/559511 [patent_app_country] => US [patent_app_date] => 1995-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4239 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646075.pdf [firstpage_image] =>[orig_patent_app_number] => 559511 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/559511
Method for optimizing thermal budgets in fabricating semiconductors Nov 14, 1995 Issued
Array ( [id] => 3589440 [patent_doc_number] => 05567631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology' [patent_app_type] => 1 [patent_app_number] => 8/557654 [patent_app_country] => US [patent_app_date] => 1995-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2127 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/567/05567631.pdf [firstpage_image] =>[orig_patent_app_number] => 557654 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/557654
Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology Nov 12, 1995 Issued
Array ( [id] => 3725590 [patent_doc_number] => 05700728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Method of forming an MNOS/MONOS by employing large tilt angle ion implantation underneath the field oxide' [patent_app_type] => 1 [patent_app_number] => 8/557695 [patent_app_country] => US [patent_app_date] => 1995-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/700/05700728.pdf [firstpage_image] =>[orig_patent_app_number] => 557695 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/557695
Method of forming an MNOS/MONOS by employing large tilt angle ion implantation underneath the field oxide Nov 12, 1995 Issued
Array ( [id] => 3632816 [patent_doc_number] => 05610087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer' [patent_app_type] => 1 [patent_app_number] => 8/565202 [patent_app_country] => US [patent_app_date] => 1995-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610087.pdf [firstpage_image] =>[orig_patent_app_number] => 565202 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565202
Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer Nov 8, 1995 Issued
Array ( [id] => 3868097 [patent_doc_number] => 05837619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Method of fabricating semiconductor device and method of processing substrate' [patent_app_type] => 1 [patent_app_number] => 8/552678 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 67 [patent_no_of_words] => 23820 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/837/05837619.pdf [firstpage_image] =>[orig_patent_app_number] => 552678 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/552678
Method of fabricating semiconductor device and method of processing substrate Nov 2, 1995 Issued
Array ( [id] => 3619586 [patent_doc_number] => 05614423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method for fabricating a heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/552778 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4435 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614423.pdf [firstpage_image] =>[orig_patent_app_number] => 552778 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/552778
Method for fabricating a heterojunction bipolar transistor Nov 2, 1995 Issued
Array ( [id] => 4000883 [patent_doc_number] => 05858853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method for forming capacitor electrode having jagged surface' [patent_app_type] => 1 [patent_app_number] => 8/550624 [patent_app_country] => US [patent_app_date] => 1995-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 4501 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/858/05858853.pdf [firstpage_image] =>[orig_patent_app_number] => 550624 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/550624
Method for forming capacitor electrode having jagged surface Oct 30, 1995 Issued
Array ( [id] => 3725304 [patent_doc_number] => 05700709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Method for manufacturing a capacitor for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/547901 [patent_app_country] => US [patent_app_date] => 1995-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 4446 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/700/05700709.pdf [firstpage_image] =>[orig_patent_app_number] => 547901 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/547901
Method for manufacturing a capacitor for a semiconductor device Oct 24, 1995 Issued
Array ( [id] => 3727872 [patent_doc_number] => 05652153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Method of making JFET structures for semiconductor devices with complementary bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/543754 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2987 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652153.pdf [firstpage_image] =>[orig_patent_app_number] => 543754 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543754
Method of making JFET structures for semiconductor devices with complementary bipolar transistors Oct 15, 1995 Issued
Array ( [id] => 3622652 [patent_doc_number] => 05612234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Method for manufacturing a thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/539156 [patent_app_country] => US [patent_app_date] => 1995-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 5089 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612234.pdf [firstpage_image] =>[orig_patent_app_number] => 539156 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/539156
Method for manufacturing a thin film transistor Oct 3, 1995 Issued
Array ( [id] => 3877187 [patent_doc_number] => 05728631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Method for forming a low capacitance dielectric layer' [patent_app_type] => 1 [patent_app_number] => 8/537106 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3325 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/728/05728631.pdf [firstpage_image] =>[orig_patent_app_number] => 537106 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/537106
Method for forming a low capacitance dielectric layer Sep 28, 1995 Issued
Array ( [id] => 4062845 [patent_doc_number] => 05866462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Double-spacer technique for forming a bipolar transistor with a very narrow emitter' [patent_app_type] => 1 [patent_app_number] => 8/536338 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1478 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866462.pdf [firstpage_image] =>[orig_patent_app_number] => 536338 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536338
Double-spacer technique for forming a bipolar transistor with a very narrow emitter Sep 28, 1995 Issued
Array ( [id] => 3686850 [patent_doc_number] => 05643808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Process of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/535892 [patent_app_country] => US [patent_app_date] => 1995-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 3213 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643808.pdf [firstpage_image] =>[orig_patent_app_number] => 535892 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/535892
Process of manufacturing a semiconductor device Sep 27, 1995 Issued
Array ( [id] => 3681709 [patent_doc_number] => 05633181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Fabrication method of semiconductor integrated circuit device having capacitors, bipolar transistors and igfets' [patent_app_type] => 1 [patent_app_number] => 8/535836 [patent_app_country] => US [patent_app_date] => 1995-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7105 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633181.pdf [firstpage_image] =>[orig_patent_app_number] => 535836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/535836
Fabrication method of semiconductor integrated circuit device having capacitors, bipolar transistors and igfets Sep 27, 1995 Issued
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