Hua Jasmine Song

Array ( [id] => 3553181 [patent_doc_number] => 05518963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Method for forming metal interconnection of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/499270 [patent_app_country] => US [patent_app_date] => 1995-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 967 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/518/05518963.pdf [firstpage_image] =>[orig_patent_app_number] => 499270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3529598 [patent_doc_number] => 05583070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Process to form rugged polycrystalline silicon surfaces' [patent_app_type] => 1 [patent_app_number] => 8/499744 [patent_app_country] => US [patent_app_date] => 1995-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2373 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583070.pdf [firstpage_image] =>[orig_patent_app_number] => 499744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3607923 [patent_doc_number] => 05589408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method of forming an alloyed drain field effect transistor and device formed' [patent_app_type] => 1 [patent_app_number] => 8/498158 [patent_app_country] => US [patent_app_date] => 1995-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3271 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589408.pdf [firstpage_image] =>[orig_patent_app_number] => 498158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3518996 [patent_doc_number] => 05529946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Process of fabricating DRAM storage capacitors' [patent_app_type] => 1 [patent_app_number] => 8/497270 [patent_app_country] => US [patent_app_date] => 1995-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2551 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/529/05529946.pdf [firstpage_image] =>[orig_patent_app_number] => 497270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3538034 [patent_doc_number] => 05494843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Method for forming MOSFET devices' [patent_app_type] => 1 [patent_app_number] => 8/496020 [patent_app_country] => US [patent_app_date] => 1995-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2692 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/494/05494843.pdf [firstpage_image] =>[orig_patent_app_number] => 496020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3705271 [patent_doc_number] => 05654223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Method for fabricating semiconductor memory element' [patent_app_type] => 1 [patent_app_number] => 8/495270 [patent_app_country] => US [patent_app_date] => 1995-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 36 [patent_no_of_words] => 4083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654223.pdf [firstpage_image] =>[orig_patent_app_number] => 495270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3695722 [patent_doc_number] => 05595931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Method for fabricating capacitor of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/491702 [patent_app_country] => US [patent_app_date] => 1995-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1349 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/595/05595931.pdf [firstpage_image] =>[orig_patent_app_number] => 491702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873236 [patent_doc_number] => 05824593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Method for making a capacitor on a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/489118 [patent_app_country] => US [patent_app_date] => 1995-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 43 [patent_no_of_words] => 3060 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/824/05824593.pdf [firstpage_image] =>[orig_patent_app_number] => 489118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3869700 [patent_doc_number] => 05763292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method of making a solid state imager with reduced smear' [patent_app_type] => 1 [patent_app_number] => 8/484892 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 68 [patent_no_of_words] => 14554 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/763/05763292.pdf [firstpage_image] =>[orig_patent_app_number] => 484892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3549449 [patent_doc_number] => 05571732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Method for fabricating a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/474272 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4515 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/571/05571732.pdf [firstpage_image] =>[orig_patent_app_number] => 474272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3608021 [patent_doc_number] => 05589415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method for forming a semiconductor structure with self-aligned contacts' [patent_app_type] => 1 [patent_app_number] => 8/472336 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3656 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589415.pdf [firstpage_image] =>[orig_patent_app_number] => 472336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3532869 [patent_doc_number] => 05556803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Method for fabricating a charge coupled device' [patent_app_type] => 1 [patent_app_number] => 8/480720 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2711 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/556/05556803.pdf [firstpage_image] =>[orig_patent_app_number] => 480720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4183248 [patent_doc_number] => 06159816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method of fabricating a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/482034 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4171 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159816.pdf [firstpage_image] =>[orig_patent_app_number] => 482034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3657891 [patent_doc_number] => 05591662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Method of manufacturing a power integrated circuit (PIC) structure' [patent_app_type] => 1 [patent_app_number] => 8/471902 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3504 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/591/05591662.pdf [firstpage_image] =>[orig_patent_app_number] => 471902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3697068 [patent_doc_number] => 05677220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/478110 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 4869 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677220.pdf [firstpage_image] =>[orig_patent_app_number] => 478110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3734516 [patent_doc_number] => 05698460 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Method of self-aligning an emitter contact in a planar heterojunction bipolar transistor and apparatus thereof' [patent_app_type] => 1 [patent_app_number] => 8/480290 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1381 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698460.pdf [firstpage_image] =>[orig_patent_app_number] => 480290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3506034 [patent_doc_number] => 05569612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Process for manufacturing a bipolar power transistor having a high breakdown voltage' [patent_app_type] => 1 [patent_app_number] => 8/481890 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/569/05569612.pdf [firstpage_image] =>[orig_patent_app_number] => 481890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3894408 [patent_doc_number] => 05750416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method of forming a lateral field effect transistor having reduced drain-to-source on-resistance' [patent_app_type] => 1 [patent_app_number] => 8/479308 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2388 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/750/05750416.pdf [firstpage_image] =>[orig_patent_app_number] => 479308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3633517 [patent_doc_number] => 05631183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Method of reducing word line resistance of a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/473984 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2353 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631183.pdf [firstpage_image] =>[orig_patent_app_number] => 473984 [rel_patent_id] =>[rel_patent_doc_number] =>)