| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3532706
[patent_doc_number] => 05556792
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-17
[patent_title] => 'Process for manufacturing a power integrated circuit (\"PIC\") structure with a vertical IGBT'
[patent_app_type] => 1
[patent_app_number] => 8/472196
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/556/05556792.pdf
[firstpage_image] =>[orig_patent_app_number] => 472196
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/472196 | Process for manufacturing a power integrated circuit ("PIC") structure with a vertical IGBT | Jun 6, 1995 | Issued |
Array
(
[id] => 3622947
[patent_doc_number] => 05607867
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-04
[patent_title] => 'Method of forming a controlled low collector breakdown voltage transistor for ESD protection circuits'
[patent_app_type] => 1
[patent_app_number] => 8/475268
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/607/05607867.pdf
[firstpage_image] =>[orig_patent_app_number] => 475268
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/475268 | Method of forming a controlled low collector breakdown voltage transistor for ESD protection circuits | Jun 6, 1995 | Issued |
Array
(
[id] => 3884995
[patent_doc_number] => 05723349
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Process for manufacturing a high conductivity insulated gate bipolar transistor integrater structure'
[patent_app_type] => 1
[patent_app_number] => 8/475070
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/723/05723349.pdf
[firstpage_image] =>[orig_patent_app_number] => 475070
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/475070 | Process for manufacturing a high conductivity insulated gate bipolar transistor integrater structure | Jun 6, 1995 | Issued |
Array
(
[id] => 3660068
[patent_doc_number] => 05648278
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Method for fabricating microwave heterojunction bipolar transistors suitable for low-power, low-noise and high-power applications'
[patent_app_type] => 1
[patent_app_number] => 8/473164
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4407
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/648/05648278.pdf
[firstpage_image] =>[orig_patent_app_number] => 473164
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/473164 | Method for fabricating microwave heterojunction bipolar transistors suitable for low-power, low-noise and high-power applications | Jun 6, 1995 | Issued |
| 08/487838 | METHOD FOR FORMING A POWER MOS DEVICE CHIP | Jun 6, 1995 | Abandoned |
Array
(
[id] => 3694673
[patent_doc_number] => 05661069
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-26
[patent_title] => 'Method of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve space'
[patent_app_type] => 1
[patent_app_number] => 8/475028
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 2412
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[pdf_file] => patents/05/661/05661069.pdf
[firstpage_image] =>[orig_patent_app_number] => 475028
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/475028 | Method of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve space | Jun 5, 1995 | Issued |
| 08/468958 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | Jun 5, 1995 | Abandoned |
Array
(
[id] => 3632804
[patent_doc_number] => 05610086
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Method of making an AlPSb/InP single heterojunction bipolar transistor on InP substrate for high-speed, high-power applications'
[patent_app_type] => 1
[patent_app_number] => 8/468584
[patent_app_country] => US
[patent_app_date] => 1995-06-06
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/610/05610086.pdf
[firstpage_image] =>[orig_patent_app_number] => 468584
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/468584 | Method of making an AlPSb/InP single heterojunction bipolar transistor on InP substrate for high-speed, high-power applications | Jun 5, 1995 | Issued |
Array
(
[id] => 3649286
[patent_doc_number] => 05605850
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-25
[patent_title] => 'Method for making a low-noise bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 8/471084
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2672
[patent_no_of_claims] => 18
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/605/05605850.pdf
[firstpage_image] =>[orig_patent_app_number] => 471084
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/471084 | Method for making a low-noise bipolar transistor | Jun 5, 1995 | Issued |
Array
(
[id] => 3730915
[patent_doc_number] => 05665626
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Method of making a chimney capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/464432
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3595
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/665/05665626.pdf
[firstpage_image] =>[orig_patent_app_number] => 464432
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/464432 | Method of making a chimney capacitor | Jun 4, 1995 | Issued |
Array
(
[id] => 3529480
[patent_doc_number] => 05583061
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'PMOS transistors with different breakdown voltages formed in the same substrate'
[patent_app_type] => 1
[patent_app_number] => 8/464435
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583061.pdf
[firstpage_image] =>[orig_patent_app_number] => 464435
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/464435 | PMOS transistors with different breakdown voltages formed in the same substrate | Jun 4, 1995 | Issued |
Array
(
[id] => 3694598
[patent_doc_number] => 05618743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-08
[patent_title] => 'MOS transistor having adjusted threshold voltage formed along with other transistors'
[patent_app_type] => 1
[patent_app_number] => 8/463417
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
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[pdf_file] => patents/05/618/05618743.pdf
[firstpage_image] =>[orig_patent_app_number] => 463417
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/463417 | MOS transistor having adjusted threshold voltage formed along with other transistors | Jun 4, 1995 | Issued |
Array
(
[id] => 3685687
[patent_doc_number] => 05663089
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Method for producing a laminated thin film capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/465350
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 7066
[patent_no_of_claims] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/663/05663089.pdf
[firstpage_image] =>[orig_patent_app_number] => 465350
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/465350 | Method for producing a laminated thin film capacitor | Jun 4, 1995 | Issued |
| 08/463137 | BICDMOS PROCESS TECHNOLOGY AND STRUCTURES | Jun 4, 1995 | Abandoned |
Array
(
[id] => 3525818
[patent_doc_number] => 05541125
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Method for forming a lateral MOS transistor having lightly doped drain formed along with other transistors in the same substrate'
[patent_app_type] => 1
[patent_app_number] => 8/463165
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
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[pdf_file] => patents/05/541/05541125.pdf
[firstpage_image] =>[orig_patent_app_number] => 463165
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/463165 | Method for forming a lateral MOS transistor having lightly doped drain formed along with other transistors in the same substrate | Jun 4, 1995 | Issued |
Array
(
[id] => 3549518
[patent_doc_number] => 05547880
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Method for forming a zener diode region and an isolation region'
[patent_app_type] => 1
[patent_app_number] => 8/464978
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
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[pdf_file] => patents/05/547/05547880.pdf
[firstpage_image] =>[orig_patent_app_number] => 464978
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/464978 | Method for forming a zener diode region and an isolation region | Jun 4, 1995 | Issued |
Array
(
[id] => 3525787
[patent_doc_number] => 05541123
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Method for forming a bipolar transistor having selected breakdown voltage'
[patent_app_type] => 1
[patent_app_number] => 8/463647
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
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[pdf_file] => patents/05/541/05541123.pdf
[firstpage_image] =>[orig_patent_app_number] => 463647
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/463647 | Method for forming a bipolar transistor having selected breakdown voltage | Jun 4, 1995 | Issued |
| 08/463403 | BICDMOS PROCESS TECHNOLOGY AND STRUCTURES | Jun 4, 1995 | Abandoned |
Array
(
[id] => 3622928
[patent_doc_number] => 05607866
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-04
[patent_title] => 'Method of fabricating a semiconductor device having silicide layers for electrodes'
[patent_app_type] => 1
[patent_app_number] => 8/458112
[patent_app_country] => US
[patent_app_date] => 1995-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 12094
[patent_no_of_claims] => 15
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/607/05607866.pdf
[firstpage_image] =>[orig_patent_app_number] => 458112
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/458112 | Method of fabricating a semiconductor device having silicide layers for electrodes | Jun 1, 1995 | Issued |
| 08/460302 | BIPOLAR SILICON-ON-INSULATOR STRUCTURE AND PROCESS | Jun 1, 1995 | Abandoned |