Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3824293 [patent_doc_number] => 05731219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Process for fabricating a semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/458616 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 46 [patent_no_of_words] => 63167 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731219.pdf [firstpage_image] =>[orig_patent_app_number] => 458616 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/458616
Process for fabricating a semiconductor integrated circuit device Jun 1, 1995 Issued
Array ( [id] => 3734503 [patent_doc_number] => 05698459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Fabrication of bipolar transistors using selective doping to improve performance characteristics' [patent_app_type] => 1 [patent_app_number] => 8/456446 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 9334 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698459.pdf [firstpage_image] =>[orig_patent_app_number] => 456446 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/456446
Fabrication of bipolar transistors using selective doping to improve performance characteristics May 31, 1995 Issued
Array ( [id] => 3692909 [patent_doc_number] => 05679587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Method of fabricating an integrated circuit with vertical bipolar power transistors and isolated lateral bipolar control transistors' [patent_app_type] => 1 [patent_app_number] => 8/455492 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4435 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/679/05679587.pdf [firstpage_image] =>[orig_patent_app_number] => 455492 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/455492
Method of fabricating an integrated circuit with vertical bipolar power transistors and isolated lateral bipolar control transistors May 30, 1995 Issued
08/453708 METHOD FOR MANUFACTURING A BIPOLAR JUNCTION TRANSISTOR HAVING A POLYSILICON EMITTER May 29, 1995 Abandoned
Array ( [id] => 3657799 [patent_doc_number] => 05591656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Semiconductor integrated circuit device with self-aligned superhigh speed bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/454410 [patent_app_country] => US [patent_app_date] => 1995-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 8341 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/591/05591656.pdf [firstpage_image] =>[orig_patent_app_number] => 454410 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/454410
Semiconductor integrated circuit device with self-aligned superhigh speed bipolar transistor May 29, 1995 Issued
Array ( [id] => 3855706 [patent_doc_number] => 05705420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method of producing a fin-shaped capacitor' [patent_app_type] => 1 [patent_app_number] => 8/451904 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 78 [patent_no_of_words] => 11122 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705420.pdf [firstpage_image] =>[orig_patent_app_number] => 451904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/451904
Method of producing a fin-shaped capacitor May 25, 1995 Issued
Array ( [id] => 3697360 [patent_doc_number] => 05677240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method for forming a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/453560 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4943 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677240.pdf [firstpage_image] =>[orig_patent_app_number] => 453560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/453560
Method for forming a semiconductor device May 25, 1995 Issued
Array ( [id] => 3566719 [patent_doc_number] => 05484747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Selective metal wiring and plug process' [patent_app_type] => 1 [patent_app_number] => 8/450418 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2777 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/484/05484747.pdf [firstpage_image] =>[orig_patent_app_number] => 450418 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/450418
Selective metal wiring and plug process May 24, 1995 Issued
Array ( [id] => 3521941 [patent_doc_number] => 05489546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process' [patent_app_type] => 1 [patent_app_number] => 8/449300 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2501 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489546.pdf [firstpage_image] =>[orig_patent_app_number] => 449300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/449300
Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process May 23, 1995 Issued
08/447490 MULTI-STAGE SEMICONDUCTOR CAVITY FILLING PROCESS May 22, 1995 Abandoned
Array ( [id] => 3601635 [patent_doc_number] => 05578523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Method for forming inlaid interconnects in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/444184 [patent_app_country] => US [patent_app_date] => 1995-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4579 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/578/05578523.pdf [firstpage_image] =>[orig_patent_app_number] => 444184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/444184
Method for forming inlaid interconnects in a semiconductor device May 17, 1995 Issued
08/442445 METHOD FOR MANUFACTURING A CAPACITOR FOR A SEMICONDUCTOR DEVICE May 15, 1995 Abandoned
Array ( [id] => 3664387 [patent_doc_number] => 05597742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Semiconductor device and method' [patent_app_type] => 1 [patent_app_number] => 8/442015 [patent_app_country] => US [patent_app_date] => 1995-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2263 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/597/05597742.pdf [firstpage_image] =>[orig_patent_app_number] => 442015 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/442015
Semiconductor device and method May 15, 1995 Issued
Array ( [id] => 3549464 [patent_doc_number] => 05571733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Method of forming CMOS integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 8/440222 [patent_app_country] => US [patent_app_date] => 1995-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2938 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/571/05571733.pdf [firstpage_image] =>[orig_patent_app_number] => 440222 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/440222
Method of forming CMOS integrated circuitry May 11, 1995 Issued
Array ( [id] => 3552845 [patent_doc_number] => 05518938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Process for fabricating a CMOS transistor having high-voltage metal-gate' [patent_app_type] => 1 [patent_app_number] => 8/435074 [patent_app_country] => US [patent_app_date] => 1995-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2302 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/518/05518938.pdf [firstpage_image] =>[orig_patent_app_number] => 435074 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435074
Process for fabricating a CMOS transistor having high-voltage metal-gate May 7, 1995 Issued
Array ( [id] => 3700045 [patent_doc_number] => 05646051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Process for forming a magnetoresistive sensor for a reading head' [patent_app_type] => 1 [patent_app_number] => 8/435254 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1815 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646051.pdf [firstpage_image] =>[orig_patent_app_number] => 435254 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435254
Process for forming a magnetoresistive sensor for a reading head May 4, 1995 Issued
Array ( [id] => 3622361 [patent_doc_number] => 05602056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Method for forming reliable MOS devices using silicon rich plasma oxide film' [patent_app_type] => 1 [patent_app_number] => 8/434528 [patent_app_country] => US [patent_app_date] => 1995-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2758 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602056.pdf [firstpage_image] =>[orig_patent_app_number] => 434528 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/434528
Method for forming reliable MOS devices using silicon rich plasma oxide film May 3, 1995 Issued
Array ( [id] => 3730061 [patent_doc_number] => 05635424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'High-density bond pad layout arrangements for semiconductor dies, and connecting to the bond pads' [patent_app_type] => 1 [patent_app_number] => 8/430399 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 9465 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635424.pdf [firstpage_image] =>[orig_patent_app_number] => 430399 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/430399
High-density bond pad layout arrangements for semiconductor dies, and connecting to the bond pads Apr 27, 1995 Issued
Array ( [id] => 3570662 [patent_doc_number] => 05538908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Method for manufacturing a BiCMOS semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/429906 [patent_app_country] => US [patent_app_date] => 1995-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 2520 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/538/05538908.pdf [firstpage_image] =>[orig_patent_app_number] => 429906 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/429906
Method for manufacturing a BiCMOS semiconductor device Apr 26, 1995 Issued
Array ( [id] => 3574293 [patent_doc_number] => 05523245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Process for fabricating high-performance facet-free small-sized bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/427844 [patent_app_country] => US [patent_app_date] => 1995-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4708 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523245.pdf [firstpage_image] =>[orig_patent_app_number] => 427844 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/427844
Process for fabricating high-performance facet-free small-sized bipolar transistor Apr 25, 1995 Issued
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