Hua Jasmine Song

Array ( [id] => 3556585 [patent_doc_number] => 05501997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Process of fabricating semiconductor devices having lightly-doped drain' [patent_app_type] => 1 [patent_app_number] => 8/425695 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1269 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/501/05501997.pdf [firstpage_image] =>[orig_patent_app_number] => 425695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3564774 [patent_doc_number] => 05482873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Method for fabricating a bipolar power transistor' [patent_app_type] => 1 [patent_app_number] => 8/422572 [patent_app_country] => US [patent_app_date] => 1995-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1337 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/482/05482873.pdf [firstpage_image] =>[orig_patent_app_number] => 422572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3521873 [patent_doc_number] => 05489541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Process of fabricating a bipolar junction transistor' [patent_app_type] => 1 [patent_app_number] => 8/422568 [patent_app_country] => US [patent_app_date] => 1995-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2040 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489541.pdf [firstpage_image] =>[orig_patent_app_number] => 422568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3581360 [patent_doc_number] => 05580802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Silicon-on-insulator gate-all-around mosfet fabrication methods' [patent_app_type] => 1 [patent_app_number] => 8/422196 [patent_app_country] => US [patent_app_date] => 1995-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3886 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/580/05580802.pdf [firstpage_image] =>[orig_patent_app_number] => 422196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3697138 [patent_doc_number] => 05677225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Process for forming a semiconductor memory cell' [patent_app_type] => 1 [patent_app_number] => 8/420468 [patent_app_country] => US [patent_app_date] => 1995-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677225.pdf [firstpage_image] =>[orig_patent_app_number] => 420468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3649448 [patent_doc_number] => 05605862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Process for making low-leakage contacts' [patent_app_type] => 1 [patent_app_number] => 8/417326 [patent_app_country] => US [patent_app_date] => 1995-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4624 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/605/05605862.pdf [firstpage_image] =>[orig_patent_app_number] => 417326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3824624 [patent_doc_number] => 05731240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Manufacturing method for semiconductor depositing device' [patent_app_type] => 1 [patent_app_number] => 8/416487 [patent_app_country] => US [patent_app_date] => 1995-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 2606 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731240.pdf [firstpage_image] =>[orig_patent_app_number] => 416487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3525773 [patent_doc_number] => 05541122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Method of fabricating an insulated-gate bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/415832 [patent_app_country] => US [patent_app_date] => 1995-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 2879 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541122.pdf [firstpage_image] =>[orig_patent_app_number] => 415832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3580752 [patent_doc_number] => 05498567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Method for manufacturing a laterally limited, single-crystal region on a substrate and the employment thereof for the manufacture of an MOS transistor and a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/379861 [patent_app_country] => US [patent_app_date] => 1995-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5510 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/498/05498567.pdf [firstpage_image] =>[orig_patent_app_number] => 379861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3884530 [patent_doc_number] => 05776812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/413410 [patent_app_country] => US [patent_app_date] => 1995-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 39 [patent_no_of_words] => 11738 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/776/05776812.pdf [firstpage_image] =>[orig_patent_app_number] => 413410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3558452 [patent_doc_number] => 05500381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-19 [patent_title] => 'Fabrication method of field-effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/413616 [patent_app_country] => US [patent_app_date] => 1995-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 11735 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/500/05500381.pdf [firstpage_image] =>[orig_patent_app_number] => 413616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3518973 [patent_doc_number] => 05529945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Methods for fabricating a multi-bit storage cell' [patent_app_type] => 1 [patent_app_number] => 8/410869 [patent_app_country] => US [patent_app_date] => 1995-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8188 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/529/05529945.pdf [firstpage_image] =>[orig_patent_app_number] => 410869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3660913 [patent_doc_number] => 05624852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time' [patent_app_type] => 1 [patent_app_number] => 8/407714 [patent_app_country] => US [patent_app_date] => 1995-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2300 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/624/05624852.pdf [firstpage_image] =>[orig_patent_app_number] => 407714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3656468 [patent_doc_number] => 05658811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/405836 [patent_app_country] => US [patent_app_date] => 1995-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 55 [patent_no_of_words] => 7175 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/658/05658811.pdf [firstpage_image] =>[orig_patent_app_number] => 405836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3619571 [patent_doc_number] => 05614422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Process for doping two levels of a double poly bipolar transistor after formation of second poly layer' [patent_app_type] => 1 [patent_app_number] => 8/405660 [patent_app_country] => US [patent_app_date] => 1995-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 4585 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614422.pdf [firstpage_image] =>[orig_patent_app_number] => 405660 [rel_patent_id] =>[rel_patent_doc_number] =>)