Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3423828 [patent_doc_number] => 05459099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Method of fabricating sub-half-micron trenches and holes' [patent_app_type] => 1 [patent_app_number] => 8/343893 [patent_app_country] => US [patent_app_date] => 1994-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 43 [patent_no_of_words] => 9082 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459099.pdf [firstpage_image] =>[orig_patent_app_number] => 343893 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/343893
Method of fabricating sub-half-micron trenches and holes Nov 16, 1994 Issued
Array ( [id] => 3489287 [patent_doc_number] => 05439834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Method for fabricating a CMOS device with reduced number of photolithography steps' [patent_app_type] => 1 [patent_app_number] => 8/340264 [patent_app_country] => US [patent_app_date] => 1994-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 2768 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/439/05439834.pdf [firstpage_image] =>[orig_patent_app_number] => 340264 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/340264
Method for fabricating a CMOS device with reduced number of photolithography steps Nov 14, 1994 Issued
Array ( [id] => 3587642 [patent_doc_number] => 05516710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Method of forming a transistor' [patent_app_type] => 1 [patent_app_number] => 8/339184 [patent_app_country] => US [patent_app_date] => 1994-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 5178 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/516/05516710.pdf [firstpage_image] =>[orig_patent_app_number] => 339184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/339184
Method of forming a transistor Nov 9, 1994 Issued
08/334956 SUPPRESS OFF CELL LEAKAGE CURRENT OF MNOS/MONOS BY EMPLOYING LARGE TILT ANGLE ION IMPLANTATION UNDERNEATH THE FIELD OXIDE Nov 6, 1994 Abandoned
Array ( [id] => 3518886 [patent_doc_number] => 05529939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Method of making an integrated circuit with complementary isolated bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/334204 [patent_app_country] => US [patent_app_date] => 1994-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2450 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/529/05529939.pdf [firstpage_image] =>[orig_patent_app_number] => 334204 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/334204
Method of making an integrated circuit with complementary isolated bipolar transistors Nov 3, 1994 Issued
Array ( [id] => 3726730 [patent_doc_number] => 05702963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Method of forming high density electronic circuit modules' [patent_app_type] => 1 [patent_app_number] => 8/333226 [patent_app_country] => US [patent_app_date] => 1994-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 67 [patent_no_of_words] => 10163 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702963.pdf [firstpage_image] =>[orig_patent_app_number] => 333226 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/333226
Method of forming high density electronic circuit modules Nov 1, 1994 Issued
Array ( [id] => 3412372 [patent_doc_number] => 05444013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Method of forming a capacitor' [patent_app_type] => 1 [patent_app_number] => 8/333262 [patent_app_country] => US [patent_app_date] => 1994-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2497 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444013.pdf [firstpage_image] =>[orig_patent_app_number] => 333262 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/333262
Method of forming a capacitor Nov 1, 1994 Issued
Array ( [id] => 3807804 [patent_doc_number] => 05811320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method of forming image with binary lens element array' [patent_app_type] => 1 [patent_app_number] => 8/292336 [patent_app_country] => US [patent_app_date] => 1994-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 5594 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811320.pdf [firstpage_image] =>[orig_patent_app_number] => 292336 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/292336
Method of forming image with binary lens element array Oct 23, 1994 Issued
Array ( [id] => 3416836 [patent_doc_number] => 05453403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Method of beveled contact opening formation' [patent_app_type] => 1 [patent_app_number] => 8/328584 [patent_app_country] => US [patent_app_date] => 1994-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2038 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453403.pdf [firstpage_image] =>[orig_patent_app_number] => 328584 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/328584
Method of beveled contact opening formation Oct 23, 1994 Issued
Array ( [id] => 3493502 [patent_doc_number] => 05508213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Method of manufacturing a semiconductor device in which a semiconductor zone is formed through diffusion from a strip of polycrystalline silicon' [patent_app_type] => 1 [patent_app_number] => 8/326440 [patent_app_country] => US [patent_app_date] => 1994-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3776 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508213.pdf [firstpage_image] =>[orig_patent_app_number] => 326440 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/326440
Method of manufacturing a semiconductor device in which a semiconductor zone is formed through diffusion from a strip of polycrystalline silicon Oct 19, 1994 Issued
Array ( [id] => 3597838 [patent_doc_number] => 05559044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'BiCDMOS process technology' [patent_app_type] => 1 [patent_app_number] => 8/323950 [patent_app_country] => US [patent_app_date] => 1994-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 54 [patent_no_of_words] => 17970 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559044.pdf [firstpage_image] =>[orig_patent_app_number] => 323950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/323950
BiCDMOS process technology Oct 16, 1994 Issued
08/323230 BIPOLAR ALIGNMENT MARK FOR SEMICONDUCTOR DEVICE AND PROCESS FOR FORMING THE SAME Oct 13, 1994 Abandoned
Array ( [id] => 3649273 [patent_doc_number] => 05605849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Use of oblique implantation in forming base of bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/320144 [patent_app_country] => US [patent_app_date] => 1994-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 6439 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/605/05605849.pdf [firstpage_image] =>[orig_patent_app_number] => 320144 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/320144
Use of oblique implantation in forming base of bipolar transistor Oct 6, 1994 Issued
Array ( [id] => 3476059 [patent_doc_number] => 05432104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Method for fabricating a vertical bipolar transistor with reduced parasitic capacitance between base and collector regions' [patent_app_type] => 1 [patent_app_number] => 8/319638 [patent_app_country] => US [patent_app_date] => 1994-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6789 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 531 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432104.pdf [firstpage_image] =>[orig_patent_app_number] => 319638 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/319638
Method for fabricating a vertical bipolar transistor with reduced parasitic capacitance between base and collector regions Oct 6, 1994 Issued
Array ( [id] => 3523882 [patent_doc_number] => 05527723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Method for forming a dynamic contact which can be either on or off or switched therebetween' [patent_app_type] => 1 [patent_app_number] => 8/316754 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 40 [patent_no_of_words] => 9239 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/527/05527723.pdf [firstpage_image] =>[orig_patent_app_number] => 316754 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/316754
Method for forming a dynamic contact which can be either on or off or switched therebetween Oct 2, 1994 Issued
Array ( [id] => 3580823 [patent_doc_number] => 05498572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/312960 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 27 [patent_no_of_words] => 4104 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/498/05498572.pdf [firstpage_image] =>[orig_patent_app_number] => 312960 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/312960
Method of manufacturing semiconductor device Sep 29, 1994 Issued
Array ( [id] => 3554479 [patent_doc_number] => 05543333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Method for manufacturing a solar cell having combined metallization' [patent_app_type] => 1 [patent_app_number] => 8/315430 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 8 [patent_no_of_words] => 3812 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/543/05543333.pdf [firstpage_image] =>[orig_patent_app_number] => 315430 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/315430
Method for manufacturing a solar cell having combined metallization Sep 29, 1994 Issued
Array ( [id] => 3685792 [patent_doc_number] => 05663097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Method of fabricating a semiconductor device having an insulating side wall' [patent_app_type] => 1 [patent_app_number] => 8/313947 [patent_app_country] => US [patent_app_date] => 1994-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 4956 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663097.pdf [firstpage_image] =>[orig_patent_app_number] => 313947 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/313947
Method of fabricating a semiconductor device having an insulating side wall Sep 27, 1994 Issued
Array ( [id] => 3537953 [patent_doc_number] => 05494837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Method of forming semiconductor-on-insulator electronic devices by growing monocrystalline semiconducting regions from trench sidewalls' [patent_app_type] => 1 [patent_app_number] => 8/312874 [patent_app_country] => US [patent_app_date] => 1994-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 39 [patent_no_of_words] => 6356 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/494/05494837.pdf [firstpage_image] =>[orig_patent_app_number] => 312874 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/312874
Method of forming semiconductor-on-insulator electronic devices by growing monocrystalline semiconducting regions from trench sidewalls Sep 26, 1994 Issued
Array ( [id] => 3412102 [patent_doc_number] => 05443994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Method of fabricating a semiconductor device having a borosilicate glass spacer' [patent_app_type] => 1 [patent_app_number] => 8/311837 [patent_app_country] => US [patent_app_date] => 1994-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 5925 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/443/05443994.pdf [firstpage_image] =>[orig_patent_app_number] => 311837 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/311837
Method of fabricating a semiconductor device having a borosilicate glass spacer Sep 22, 1994 Issued
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