Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3427579 [patent_doc_number] => 05462894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Method for fabricating a polycrystalline silicon resistive load element in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/310925 [patent_app_country] => US [patent_app_date] => 1994-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2138 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/462/05462894.pdf [firstpage_image] =>[orig_patent_app_number] => 310925 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/310925
Method for fabricating a polycrystalline silicon resistive load element in an integrated circuit Sep 21, 1994 Issued
Array ( [id] => 3428216 [patent_doc_number] => 05455186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Method for manufacturing an offset lattice bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/309044 [patent_app_country] => US [patent_app_date] => 1994-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3458 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455186.pdf [firstpage_image] =>[orig_patent_app_number] => 309044 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/309044
Method for manufacturing an offset lattice bipolar transistor Sep 19, 1994 Issued
Array ( [id] => 3524391 [patent_doc_number] => 05504020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Method for fabricating thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/307068 [patent_app_country] => US [patent_app_date] => 1994-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8713 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504020.pdf [firstpage_image] =>[orig_patent_app_number] => 307068 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/307068
Method for fabricating thin film transistor Sep 15, 1994 Issued
Array ( [id] => 3113261 [patent_doc_number] => 05409861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Method of forming a via plug in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/305306 [patent_app_country] => US [patent_app_date] => 1994-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1169 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/409/05409861.pdf [firstpage_image] =>[orig_patent_app_number] => 305306 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/305306
Method of forming a via plug in a semiconductor device Sep 14, 1994 Issued
08/305550 ONE-CHIP INTEGRATED SENSOR PROCESS Sep 13, 1994 Abandoned
Array ( [id] => 3589074 [patent_doc_number] => 05496748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Method for producing refractory metal gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/304852 [patent_app_country] => US [patent_app_date] => 1994-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 36 [patent_no_of_words] => 5859 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/496/05496748.pdf [firstpage_image] =>[orig_patent_app_number] => 304852 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/304852
Method for producing refractory metal gate electrode Sep 12, 1994 Issued
Array ( [id] => 3543666 [patent_doc_number] => 05554545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Method of forming neuron mosfet with different interpolysilicon oxide thickness' [patent_app_type] => 1 [patent_app_number] => 8/299266 [patent_app_country] => US [patent_app_date] => 1994-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2517 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/554/05554545.pdf [firstpage_image] =>[orig_patent_app_number] => 299266 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/299266
Method of forming neuron mosfet with different interpolysilicon oxide thickness Aug 31, 1994 Issued
Array ( [id] => 3564981 [patent_doc_number] => 05482886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Method for fabricating dynamic random access memory capacitor' [patent_app_type] => 1 [patent_app_number] => 8/297420 [patent_app_country] => US [patent_app_date] => 1994-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2706 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 454 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/482/05482886.pdf [firstpage_image] =>[orig_patent_app_number] => 297420 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/297420
Method for fabricating dynamic random access memory capacitor Aug 28, 1994 Issued
Array ( [id] => 3565101 [patent_doc_number] => 05482894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Method of fabricating a self-aligned contact using organic dielectric materials' [patent_app_type] => 1 [patent_app_number] => 8/294290 [patent_app_country] => US [patent_app_date] => 1994-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2936 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/482/05482894.pdf [firstpage_image] =>[orig_patent_app_number] => 294290 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/294290
Method of fabricating a self-aligned contact using organic dielectric materials Aug 22, 1994 Issued
Array ( [id] => 3123240 [patent_doc_number] => 05436204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Recrystallization method to selenization of thin-film Cu(In,Ga)Se.sub.2 for semiconductor device applications' [patent_app_type] => 1 [patent_app_number] => 8/293826 [patent_app_country] => US [patent_app_date] => 1994-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6574 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436204.pdf [firstpage_image] =>[orig_patent_app_number] => 293826 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/293826
Recrystallization method to selenization of thin-film Cu(In,Ga)Se.sub.2 for semiconductor device applications Aug 21, 1994 Issued
Array ( [id] => 3565008 [patent_doc_number] => 05482888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Method of manufacturing a low resistance, high breakdown voltage, power MOSFET' [patent_app_type] => 1 [patent_app_number] => 8/289630 [patent_app_country] => US [patent_app_date] => 1994-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4250 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/482/05482888.pdf [firstpage_image] =>[orig_patent_app_number] => 289630 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/289630
Method of manufacturing a low resistance, high breakdown voltage, power MOSFET Aug 11, 1994 Issued
Array ( [id] => 3447895 [patent_doc_number] => 05424231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-13 [patent_title] => 'Method for manufacturing a VDMOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/287950 [patent_app_country] => US [patent_app_date] => 1994-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 38 [patent_no_of_words] => 3440 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/424/05424231.pdf [firstpage_image] =>[orig_patent_app_number] => 287950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/287950
Method for manufacturing a VDMOS transistor Aug 8, 1994 Issued
Array ( [id] => 3726648 [patent_doc_number] => 05702958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Method for the fabrication of bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/287568 [patent_app_country] => US [patent_app_date] => 1994-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4328 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702958.pdf [firstpage_image] =>[orig_patent_app_number] => 287568 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/287568
Method for the fabrication of bipolar transistors Aug 8, 1994 Issued
Array ( [id] => 3491999 [patent_doc_number] => 05536670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Process for making a buried bit line memory cell' [patent_app_type] => 1 [patent_app_number] => 8/287722 [patent_app_country] => US [patent_app_date] => 1994-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1716 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/536/05536670.pdf [firstpage_image] =>[orig_patent_app_number] => 287722 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/287722
Process for making a buried bit line memory cell Aug 8, 1994 Issued
Array ( [id] => 3423677 [patent_doc_number] => 05459088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Method for making a thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/287750 [patent_app_country] => US [patent_app_date] => 1994-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1560 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459088.pdf [firstpage_image] =>[orig_patent_app_number] => 287750 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/287750
Method for making a thin film transistor Aug 8, 1994 Issued
Array ( [id] => 3495786 [patent_doc_number] => 05532176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Process for fabricating a complementary MIS transistor' [patent_app_type] => 1 [patent_app_number] => 8/280922 [patent_app_country] => US [patent_app_date] => 1994-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 34 [patent_no_of_words] => 9105 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532176.pdf [firstpage_image] =>[orig_patent_app_number] => 280922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280922
Process for fabricating a complementary MIS transistor Jul 25, 1994 Issued
Array ( [id] => 3478189 [patent_doc_number] => 05399511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Method of manufacturing a hetero bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/280199 [patent_app_country] => US [patent_app_date] => 1994-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5304 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399511.pdf [firstpage_image] =>[orig_patent_app_number] => 280199 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280199
Method of manufacturing a hetero bipolar transistor Jul 24, 1994 Issued
08/279024 JFET STRUCTURES FOR SEMICONDUCTOR DEVICES WITH COMPLEMENTARY BIPOLAR TRANSISTORS AND METHOD OF MAKING Jul 21, 1994 Abandoned
Array ( [id] => 1462457 [patent_doc_number] => 06350640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor' [patent_app_type] => B1 [patent_app_number] => 08/276290 [patent_app_country] => US [patent_app_date] => 1994-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3992 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350640.pdf [firstpage_image] =>[orig_patent_app_number] => 08276290 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/276290
CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor Jul 17, 1994 Issued
Array ( [id] => 3446455 [patent_doc_number] => 05387553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Method for forming a lateral bipolar transistor with dual collector, circular symmetry and composite structure' [patent_app_type] => 1 [patent_app_number] => 8/276222 [patent_app_country] => US [patent_app_date] => 1994-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2835 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387553.pdf [firstpage_image] =>[orig_patent_app_number] => 276222 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/276222
Method for forming a lateral bipolar transistor with dual collector, circular symmetry and composite structure Jul 14, 1994 Issued
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