Hua Jasmine Song

Array ( [id] => 19122618 [patent_doc_number] => 11966604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Method and apparatus for programming data arranged to undergo specific stages into flash memory based on virtual carriers [patent_app_type] => utility [patent_app_number] => 17/879182 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19340614 [patent_doc_number] => 12050805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Control of bulk memory instructions [patent_app_type] => utility [patent_app_number] => 17/875758 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19198087 [patent_doc_number] => 11995325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Modular system dynamic rendering controller [patent_app_type] => utility [patent_app_number] => 17/863477 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5841 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17984482 [patent_doc_number] => 20220350519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => MIGRATING DATA FROM A LARGE EXTENT POOL TO A SMALL EXTENT POOL [patent_app_type] => utility [patent_app_number] => 17/863077 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17962229 [patent_doc_number] => 20220342810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => MEMORY SUB-SYSTEM LOGICAL BLOCK ADDRESS REMAPPING [patent_app_type] => utility [patent_app_number] => 17/861414 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18881429 [patent_doc_number] => 20240004798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => TECHNIQUES FOR EFFICIENT USER LOG FLUSHING WITH SHORTCUT LOGICAL ADDRESS BINDING AND POSTPONING MAPPING INFORMATION UPDATES [patent_app_type] => utility [patent_app_number] => 17/856436 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17947960 [patent_doc_number] => 20220334979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => Crossbar Circuits And Methods For External Communication With Logic In Integrated Circuits [patent_app_type] => utility [patent_app_number] => 17/853772 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18864317 [patent_doc_number] => 20230418753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => ALLOCATION CONTROL FOR CACHE [patent_app_type] => utility [patent_app_number] => 17/852296 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18864039 [patent_doc_number] => 20230418475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => MEMORY OPERATION BASED ON BLOCK-ASSOCIATED TEMPERATURE [patent_app_type] => utility [patent_app_number] => 17/848061 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17931930 [patent_doc_number] => 20220327055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => ALIASED MODE FOR CACHE CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/847131 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20374010 [patent_doc_number] => 12481444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Smart NIC responding to requests from client device [patent_app_type] => utility [patent_app_number] => 17/845766 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19243353 [patent_doc_number] => 12013792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Error avoidance for partially programmed blocks of a memory device [patent_app_type] => utility [patent_app_number] => 17/842278 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20344900 [patent_doc_number] => 12468632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Method for embedding rows prefetching in recommendation models [patent_app_type] => utility [patent_app_number] => 17/835810 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17869119 [patent_doc_number] => 20220291856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SYSTEM AND METHOD FOR CONTENT ADDRESSABLE STORAGE SYSTEM UPDATE APPLIANCE [patent_app_type] => utility [patent_app_number] => 17/828416 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18832625 [patent_doc_number] => 20230401152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => PERFORMANCE AWARE PARTIAL CACHE COLLAPSE [patent_app_type] => utility [patent_app_number] => 17/827302 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18838985 [patent_doc_number] => 11847056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-19 [patent_title] => Technique for controlling use of a cache to store prefetcher metadata [patent_app_type] => utility [patent_app_number] => 17/824199 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 13268 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18810636 [patent_doc_number] => 20230384972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => TECHNIQUES FOR DETECTION OF SHUTDOWN PATTERNS [patent_app_type] => utility [patent_app_number] => 17/752354 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18755946 [patent_doc_number] => 20230359391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => ALLOCATION OF HOST MEMORY BUFFER FOR SUSTAINED SEQUENTIAL WRITES [patent_app_type] => utility [patent_app_number] => 17/737830 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18630395 [patent_doc_number] => 20230289288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => DIRECT SWAP CACHING WITH NOISY NEIGHBOR MITIGATION AND DYNAMIC ADDRESS RANGE ASSIGNMENT [patent_app_type] => utility [patent_app_number] => 17/735767 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18291386 [patent_doc_number] => 11620256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Systems and methods for improving cache efficiency and utilization [patent_app_type] => utility [patent_app_number] => 17/732308 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 64 [patent_no_of_words] => 46487 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732308 [rel_patent_id] =>[rel_patent_doc_number] =>)