Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3441095 [patent_doc_number] => 05429986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Electrode forming process' [patent_app_type] => 1 [patent_app_number] => 8/276754 [patent_app_country] => US [patent_app_date] => 1994-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1809 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/429/05429986.pdf [firstpage_image] =>[orig_patent_app_number] => 276754 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/276754
Electrode forming process Jul 13, 1994 Issued
Array ( [id] => 3556506 [patent_doc_number] => 05501991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Process for making a bipolar junction transistor with a self-aligned base contact' [patent_app_type] => 1 [patent_app_number] => 8/274540 [patent_app_country] => US [patent_app_date] => 1994-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2594 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/501/05501991.pdf [firstpage_image] =>[orig_patent_app_number] => 274540 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/274540
Process for making a bipolar junction transistor with a self-aligned base contact Jul 12, 1994 Issued
Array ( [id] => 3453053 [patent_doc_number] => 05451532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Process for making self-aligned polysilicon base contact in a bipolar junction transistor' [patent_app_type] => 1 [patent_app_number] => 8/273530 [patent_app_country] => US [patent_app_date] => 1994-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4498 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451532.pdf [firstpage_image] =>[orig_patent_app_number] => 273530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/273530
Process for making self-aligned polysilicon base contact in a bipolar junction transistor Jul 10, 1994 Issued
Array ( [id] => 3513898 [patent_doc_number] => 05512497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/272312 [patent_app_country] => US [patent_app_date] => 1994-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 11789 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/512/05512497.pdf [firstpage_image] =>[orig_patent_app_number] => 272312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/272312
Method of manufacturing a semiconductor integrated circuit device Jul 7, 1994 Issued
Array ( [id] => 3453870 [patent_doc_number] => 05378646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Process for producing closely spaced conductive lines for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/271756 [patent_app_country] => US [patent_app_date] => 1994-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/378/05378646.pdf [firstpage_image] =>[orig_patent_app_number] => 271756 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/271756
Process for producing closely spaced conductive lines for integrated circuits Jul 6, 1994 Issued
Array ( [id] => 3474458 [patent_doc_number] => 05427968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Split-gate flash memory cell with separated and self-aligned tunneling regions' [patent_app_type] => 1 [patent_app_number] => 8/269536 [patent_app_country] => US [patent_app_date] => 1994-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 2476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/427/05427968.pdf [firstpage_image] =>[orig_patent_app_number] => 269536 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/269536
Split-gate flash memory cell with separated and self-aligned tunneling regions Jun 30, 1994 Issued
Array ( [id] => 3480493 [patent_doc_number] => 05405795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Method of forming a SOI transistor having a self-aligned body contact' [patent_app_type] => 1 [patent_app_number] => 8/268380 [patent_app_country] => US [patent_app_date] => 1994-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 1723 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/405/05405795.pdf [firstpage_image] =>[orig_patent_app_number] => 268380 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/268380
Method of forming a SOI transistor having a self-aligned body contact Jun 28, 1994 Issued
Array ( [id] => 3558423 [patent_doc_number] => 05500379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-19 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/265104 [patent_app_country] => US [patent_app_date] => 1994-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 44 [patent_no_of_words] => 7022 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/500/05500379.pdf [firstpage_image] =>[orig_patent_app_number] => 265104 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/265104
Method of manufacturing semiconductor device Jun 23, 1994 Issued
Array ( [id] => 3549777 [patent_doc_number] => 05547897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Photo-assisted nitrogen doping of II-VI semiconductor compounds during epitaxial growth using an amine' [patent_app_type] => 1 [patent_app_number] => 8/259944 [patent_app_country] => US [patent_app_date] => 1994-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2775 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/547/05547897.pdf [firstpage_image] =>[orig_patent_app_number] => 259944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/259944
Photo-assisted nitrogen doping of II-VI semiconductor compounds during epitaxial growth using an amine Jun 14, 1994 Issued
Array ( [id] => 3111947 [patent_doc_number] => 05395775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Method for manufacturing lateral bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/261151 [patent_app_country] => US [patent_app_date] => 1994-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3405 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/395/05395775.pdf [firstpage_image] =>[orig_patent_app_number] => 261151 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/261151
Method for manufacturing lateral bipolar transistors Jun 13, 1994 Issued
Array ( [id] => 3106305 [patent_doc_number] => 05418180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon' [patent_app_type] => 1 [patent_app_number] => 8/259766 [patent_app_country] => US [patent_app_date] => 1994-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2403 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418180.pdf [firstpage_image] =>[orig_patent_app_number] => 259766 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/259766
Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon Jun 13, 1994 Issued
Array ( [id] => 3106972 [patent_doc_number] => 05407843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Method for manufacturing lateral bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/261142 [patent_app_country] => US [patent_app_date] => 1994-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2285 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/407/05407843.pdf [firstpage_image] =>[orig_patent_app_number] => 261142 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/261142
Method for manufacturing lateral bipolar transistors Jun 13, 1994 Issued
Array ( [id] => 3458867 [patent_doc_number] => 05441901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic' [patent_app_type] => 1 [patent_app_number] => 8/257972 [patent_app_country] => US [patent_app_date] => 1994-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3073 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/441/05441901.pdf [firstpage_image] =>[orig_patent_app_number] => 257972 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/257972
Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic Jun 9, 1994 Issued
Array ( [id] => 3574257 [patent_doc_number] => 05523243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Method of fabricating a triple heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/255696 [patent_app_country] => US [patent_app_date] => 1994-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2091 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523243.pdf [firstpage_image] =>[orig_patent_app_number] => 255696 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/255696
Method of fabricating a triple heterojunction bipolar transistor Jun 7, 1994 Issued
Array ( [id] => 3106941 [patent_doc_number] => 05407842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Enhanced performance bipolar transistor process' [patent_app_type] => 1 [patent_app_number] => 8/255502 [patent_app_country] => US [patent_app_date] => 1994-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3164 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/407/05407842.pdf [firstpage_image] =>[orig_patent_app_number] => 255502 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/255502
Enhanced performance bipolar transistor process Jun 7, 1994 Issued
Array ( [id] => 3566619 [patent_doc_number] => 05484740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Method of manufacturing a III-V semiconductor gate structure' [patent_app_type] => 1 [patent_app_number] => 8/254206 [patent_app_country] => US [patent_app_date] => 1994-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2761 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/484/05484740.pdf [firstpage_image] =>[orig_patent_app_number] => 254206 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/254206
Method of manufacturing a III-V semiconductor gate structure Jun 5, 1994 Issued
08/252088 LAMINATED WIRING STRUCTURE PREVENTING IMPURITY DIFFUSION THEREIN FROM N+ AND P+ REGIONS IN CMOS DEVICE WITH OHMIC CONTACT May 31, 1994 Abandoned
Array ( [id] => 3459105 [patent_doc_number] => 05441917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Method of laying out bond pads on a semiconductor die' [patent_app_type] => 1 [patent_app_number] => 8/251058 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 9461 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/441/05441917.pdf [firstpage_image] =>[orig_patent_app_number] => 251058 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/251058
Method of laying out bond pads on a semiconductor die May 30, 1994 Issued
Array ( [id] => 3460832 [patent_doc_number] => 05468660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Process for manufacturing an integrated bipolar power device and a fast diode' [patent_app_type] => 1 [patent_app_number] => 8/251514 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2868 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/468/05468660.pdf [firstpage_image] =>[orig_patent_app_number] => 251514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/251514
Process for manufacturing an integrated bipolar power device and a fast diode May 30, 1994 Issued
Array ( [id] => 3107287 [patent_doc_number] => 05407860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Method of forming air gap dielectric spaces between semiconductor leads' [patent_app_type] => 1 [patent_app_number] => 8/250064 [patent_app_country] => US [patent_app_date] => 1994-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1464 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/407/05407860.pdf [firstpage_image] =>[orig_patent_app_number] => 250064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/250064
Method of forming air gap dielectric spaces between semiconductor leads May 26, 1994 Issued
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