
Hua Jasmine Song
Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )
| Most Active Art Unit | 2133 |
| Art Unit(s) | 2131, 2189, 2187, 2138, 2133, 2188 |
| Total Applications | 1393 |
| Issued Applications | 1256 |
| Pending Applications | 72 |
| Abandoned Applications | 80 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3441095
[patent_doc_number] => 05429986
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Electrode forming process'
[patent_app_type] => 1
[patent_app_number] => 8/276754
[patent_app_country] => US
[patent_app_date] => 1994-07-14
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[patent_no_of_words] => 1809
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[pdf_file] => patents/05/429/05429986.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/276754 | Electrode forming process | Jul 13, 1994 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1996-03-26
[patent_title] => 'Process for making a bipolar junction transistor with a self-aligned base contact'
[patent_app_type] => 1
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[patent_app_date] => 1994-07-13
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Array
(
[id] => 3453053
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[patent_kind] => NA
[patent_issue_date] => 1995-09-19
[patent_title] => 'Process for making self-aligned polysilicon base contact in a bipolar junction transistor'
[patent_app_type] => 1
[patent_app_number] => 8/273530
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[patent_app_date] => 1994-07-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/273530 | Process for making self-aligned polysilicon base contact in a bipolar junction transistor | Jul 10, 1994 | Issued |
Array
(
[id] => 3513898
[patent_doc_number] => 05512497
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Method of manufacturing a semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/272312
[patent_app_country] => US
[patent_app_date] => 1994-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/272312 | Method of manufacturing a semiconductor integrated circuit device | Jul 7, 1994 | Issued |
Array
(
[id] => 3453870
[patent_doc_number] => 05378646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-03
[patent_title] => 'Process for producing closely spaced conductive lines for integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/271756
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[patent_app_date] => 1994-07-07
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[firstpage_image] =>[orig_patent_app_number] => 271756
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/271756 | Process for producing closely spaced conductive lines for integrated circuits | Jul 6, 1994 | Issued |
Array
(
[id] => 3474458
[patent_doc_number] => 05427968
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-27
[patent_title] => 'Split-gate flash memory cell with separated and self-aligned tunneling regions'
[patent_app_type] => 1
[patent_app_number] => 8/269536
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[pdf_file] => patents/05/427/05427968.pdf
[firstpage_image] =>[orig_patent_app_number] => 269536
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/269536 | Split-gate flash memory cell with separated and self-aligned tunneling regions | Jun 30, 1994 | Issued |
Array
(
[id] => 3480493
[patent_doc_number] => 05405795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-11
[patent_title] => 'Method of forming a SOI transistor having a self-aligned body contact'
[patent_app_type] => 1
[patent_app_number] => 8/268380
[patent_app_country] => US
[patent_app_date] => 1994-06-29
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[patent_drawing_sheets_cnt] => 4
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[firstpage_image] =>[orig_patent_app_number] => 268380
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/268380 | Method of forming a SOI transistor having a self-aligned body contact | Jun 28, 1994 | Issued |
Array
(
[id] => 3558423
[patent_doc_number] => 05500379
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-19
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/265104
[patent_app_country] => US
[patent_app_date] => 1994-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
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[pdf_file] => patents/05/500/05500379.pdf
[firstpage_image] =>[orig_patent_app_number] => 265104
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/265104 | Method of manufacturing semiconductor device | Jun 23, 1994 | Issued |
Array
(
[id] => 3549777
[patent_doc_number] => 05547897
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Photo-assisted nitrogen doping of II-VI semiconductor compounds during epitaxial growth using an amine'
[patent_app_type] => 1
[patent_app_number] => 8/259944
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[firstpage_image] =>[orig_patent_app_number] => 259944
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/259944 | Photo-assisted nitrogen doping of II-VI semiconductor compounds during epitaxial growth using an amine | Jun 14, 1994 | Issued |
Array
(
[id] => 3111947
[patent_doc_number] => 05395775
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-07
[patent_title] => 'Method for manufacturing lateral bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 8/261151
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[patent_app_date] => 1994-06-14
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[firstpage_image] =>[orig_patent_app_number] => 261151
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/261151 | Method for manufacturing lateral bipolar transistors | Jun 13, 1994 | Issued |
Array
(
[id] => 3106305
[patent_doc_number] => 05418180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-23
[patent_title] => 'Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon'
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[firstpage_image] =>[orig_patent_app_number] => 259766
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/259766 | Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon | Jun 13, 1994 | Issued |
Array
(
[id] => 3106972
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[firstpage_image] =>[orig_patent_app_number] => 261142
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Array
(
[id] => 3458867
[patent_doc_number] => 05441901
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-15
[patent_title] => 'Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic'
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[firstpage_image] =>[orig_patent_app_number] => 257972
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/257972 | Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic | Jun 9, 1994 | Issued |
Array
(
[id] => 3574257
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[patent_issue_date] => 1996-06-04
[patent_title] => 'Method of fabricating a triple heterojunction bipolar transistor'
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[firstpage_image] =>[orig_patent_app_number] => 255696
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/255696 | Method of fabricating a triple heterojunction bipolar transistor | Jun 7, 1994 | Issued |
Array
(
[id] => 3106941
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[patent_issue_date] => 1995-04-18
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Array
(
[id] => 3566619
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[patent_issue_date] => 1996-01-16
[patent_title] => 'Method of manufacturing a III-V semiconductor gate structure'
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[pdf_file] => patents/05/484/05484740.pdf
[firstpage_image] =>[orig_patent_app_number] => 254206
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/254206 | Method of manufacturing a III-V semiconductor gate structure | Jun 5, 1994 | Issued |
| 08/252088 | LAMINATED WIRING STRUCTURE PREVENTING IMPURITY DIFFUSION THEREIN FROM N+ AND P+ REGIONS IN CMOS DEVICE WITH OHMIC CONTACT | May 31, 1994 | Abandoned |
Array
(
[id] => 3459105
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[patent_title] => 'Method of laying out bond pads on a semiconductor die'
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Array
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Array
(
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