Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3453982 [patent_doc_number] => 05378654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Self-aligned contact process' [patent_app_type] => 1 [patent_app_number] => 8/249306 [patent_app_country] => US [patent_app_date] => 1994-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2646 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/378/05378654.pdf [firstpage_image] =>[orig_patent_app_number] => 249306 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/249306
Self-aligned contact process May 23, 1994 Issued
Array ( [id] => 3587758 [patent_doc_number] => 05516719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Method for the fabrication of a capacitor in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/247864 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1938 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/516/05516719.pdf [firstpage_image] =>[orig_patent_app_number] => 247864 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247864
Method for the fabrication of a capacitor in a semiconductor device May 22, 1994 Issued
Array ( [id] => 3102137 [patent_doc_number] => 05447881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Method for the fabrication of capacitor in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/247238 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1759 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/447/05447881.pdf [firstpage_image] =>[orig_patent_app_number] => 247238 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247238
Method for the fabrication of capacitor in semiconductor device May 22, 1994 Issued
Array ( [id] => 3117477 [patent_doc_number] => 05380676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Method of manufacturing a high density ROM' [patent_app_type] => 1 [patent_app_number] => 8/247680 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 4814 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/380/05380676.pdf [firstpage_image] =>[orig_patent_app_number] => 247680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247680
Method of manufacturing a high density ROM May 22, 1994 Issued
Array ( [id] => 3421896 [patent_doc_number] => 05389563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Method of fabricating a bipolar transistor having a high ion concentration buried floating collector' [patent_app_type] => 1 [patent_app_number] => 8/242604 [patent_app_country] => US [patent_app_date] => 1994-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 2596 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/389/05389563.pdf [firstpage_image] =>[orig_patent_app_number] => 242604 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/242604
Method of fabricating a bipolar transistor having a high ion concentration buried floating collector May 12, 1994 Issued
Array ( [id] => 3570646 [patent_doc_number] => 05538907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Method for forming a CMOS integrated circuit with electrostatic discharge protection' [patent_app_type] => 1 [patent_app_number] => 8/241358 [patent_app_country] => US [patent_app_date] => 1994-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5593 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/538/05538907.pdf [firstpage_image] =>[orig_patent_app_number] => 241358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/241358
Method for forming a CMOS integrated circuit with electrostatic discharge protection May 10, 1994 Issued
08/237064 SEMICONDUCTOR DEVICES HAVING LIGHTLY-DOPED DRAIN AND THE PROCESS OF FABRICATING THE SAME May 2, 1994 Abandoned
Array ( [id] => 3480354 [patent_doc_number] => 05457059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Method for forming TiW fuses in high performance BiCMOS process' [patent_app_type] => 1 [patent_app_number] => 8/234894 [patent_app_country] => US [patent_app_date] => 1994-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2297 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457059.pdf [firstpage_image] =>[orig_patent_app_number] => 234894 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/234894
Method for forming TiW fuses in high performance BiCMOS process Apr 27, 1994 Issued
Array ( [id] => 2993755 [patent_doc_number] => 05362659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Method for fabricating vertical bipolar junction transistors in silicon bonded to an insulator' [patent_app_type] => 1 [patent_app_number] => 8/232914 [patent_app_country] => US [patent_app_date] => 1994-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 3800 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/362/05362659.pdf [firstpage_image] =>[orig_patent_app_number] => 232914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/232914
Method for fabricating vertical bipolar junction transistors in silicon bonded to an insulator Apr 24, 1994 Issued
Array ( [id] => 3440747 [patent_doc_number] => 05429963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Twin-tub complementary heterostructure field effect transistor fab process' [patent_app_type] => 1 [patent_app_number] => 8/232978 [patent_app_country] => US [patent_app_date] => 1994-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1939 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/429/05429963.pdf [firstpage_image] =>[orig_patent_app_number] => 232978 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/232978
Twin-tub complementary heterostructure field effect transistor fab process Apr 24, 1994 Issued
Array ( [id] => 3122794 [patent_doc_number] => 05436181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Method of self aligning an emitter contact in a heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/229044 [patent_app_country] => US [patent_app_date] => 1994-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1914 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436181.pdf [firstpage_image] =>[orig_patent_app_number] => 229044 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/229044
Method of self aligning an emitter contact in a heterojunction bipolar transistor Apr 17, 1994 Issued
Array ( [id] => 3564804 [patent_doc_number] => 05482875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Method for forming a linear heterojunction field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/229266 [patent_app_country] => US [patent_app_date] => 1994-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5723 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/482/05482875.pdf [firstpage_image] =>[orig_patent_app_number] => 229266 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/229266
Method for forming a linear heterojunction field effect transistor Apr 17, 1994 Issued
Array ( [id] => 3106989 [patent_doc_number] => 05407844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Process for simultaneously fabricating an insulated gate field-effect transistor and a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/228164 [patent_app_country] => US [patent_app_date] => 1994-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 99 [patent_no_of_words] => 26342 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/407/05407844.pdf [firstpage_image] =>[orig_patent_app_number] => 228164 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/228164
Process for simultaneously fabricating an insulated gate field-effect transistor and a bipolar transistor Apr 14, 1994 Issued
Array ( [id] => 3412247 [patent_doc_number] => 05444004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'CMOS process compatible self-alignment lateral bipolar junction transistor' [patent_app_type] => 1 [patent_app_number] => 8/227358 [patent_app_country] => US [patent_app_date] => 1994-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2694 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444004.pdf [firstpage_image] =>[orig_patent_app_number] => 227358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/227358
CMOS process compatible self-alignment lateral bipolar junction transistor Apr 12, 1994 Issued
Array ( [id] => 3409903 [patent_doc_number] => 05438005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Deep collection guard ring' [patent_app_type] => 1 [patent_app_number] => 8/227356 [patent_app_country] => US [patent_app_date] => 1994-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3424 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438005.pdf [firstpage_image] =>[orig_patent_app_number] => 227356 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/227356
Deep collection guard ring Apr 12, 1994 Issued
Array ( [id] => 3492739 [patent_doc_number] => 05561073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Method of fabricating an isolation trench for analog bipolar devices in harsh environments' [patent_app_type] => 1 [patent_app_number] => 8/226804 [patent_app_country] => US [patent_app_date] => 1994-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 4086 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561073.pdf [firstpage_image] =>[orig_patent_app_number] => 226804 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/226804
Method of fabricating an isolation trench for analog bipolar devices in harsh environments Apr 11, 1994 Issued
Array ( [id] => 3038511 [patent_doc_number] => 05376564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Method of manufacturing a bipolar transistor having a decreased collector-base capacitance' [patent_app_type] => 1 [patent_app_number] => 8/220918 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 4336 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 869 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/376/05376564.pdf [firstpage_image] =>[orig_patent_app_number] => 220918 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/220918
Method of manufacturing a bipolar transistor having a decreased collector-base capacitance Mar 30, 1994 Issued
Array ( [id] => 3480522 [patent_doc_number] => 05405797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Method of producing a monolithically integrated millimeter wave circuit' [patent_app_type] => 1 [patent_app_number] => 8/219856 [patent_app_country] => US [patent_app_date] => 1994-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3509 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/405/05405797.pdf [firstpage_image] =>[orig_patent_app_number] => 219856 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/219856
Method of producing a monolithically integrated millimeter wave circuit Mar 29, 1994 Issued
Array ( [id] => 3416849 [patent_doc_number] => 05453404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Method for making an interconnection structure for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/217410 [patent_app_country] => US [patent_app_date] => 1994-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4042 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453404.pdf [firstpage_image] =>[orig_patent_app_number] => 217410 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/217410
Method for making an interconnection structure for integrated circuits Mar 23, 1994 Issued
Array ( [id] => 3453039 [patent_doc_number] => 05451531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Method of fabricating an insulated gate semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/215712 [patent_app_country] => US [patent_app_date] => 1994-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 11923 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451531.pdf [firstpage_image] =>[orig_patent_app_number] => 215712 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/215712
Method of fabricating an insulated gate semiconductor device Mar 21, 1994 Issued
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