Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3038495 [patent_doc_number] => 05376563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Method of manufacturing an emitter base self alignment structure' [patent_app_type] => 1 [patent_app_number] => 8/210267 [patent_app_country] => US [patent_app_date] => 1994-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 1955 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/376/05376563.pdf [firstpage_image] =>[orig_patent_app_number] => 210267 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/210267
Method of manufacturing an emitter base self alignment structure Mar 17, 1994 Issued
Array ( [id] => 3428354 [patent_doc_number] => 05455196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Method of forming an array of electron emitters' [patent_app_type] => 1 [patent_app_number] => 8/214926 [patent_app_country] => US [patent_app_date] => 1994-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455196.pdf [firstpage_image] =>[orig_patent_app_number] => 214926 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/214926
Method of forming an array of electron emitters Mar 16, 1994 Issued
Array ( [id] => 3415299 [patent_doc_number] => 05393681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Method for forming a compact transistor structure' [patent_app_type] => 1 [patent_app_number] => 8/215888 [patent_app_country] => US [patent_app_date] => 1994-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 40 [patent_no_of_words] => 9121 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/393/05393681.pdf [firstpage_image] =>[orig_patent_app_number] => 215888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/215888
Method for forming a compact transistor structure Mar 14, 1994 Issued
Array ( [id] => 3410901 [patent_doc_number] => 05411900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-02 [patent_title] => 'Method of fabricating a monolithic integrated circuit with at least one CMOS field-effect transistor and one NPN bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/206066 [patent_app_country] => US [patent_app_date] => 1994-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 1838 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/411/05411900.pdf [firstpage_image] =>[orig_patent_app_number] => 206066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/206066
Method of fabricating a monolithic integrated circuit with at least one CMOS field-effect transistor and one NPN bipolar transistor Mar 3, 1994 Issued
Array ( [id] => 3415412 [patent_doc_number] => 05393689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Process for forming a static-random-access memory cell' [patent_app_type] => 1 [patent_app_number] => 8/209170 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6217 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/393/05393689.pdf [firstpage_image] =>[orig_patent_app_number] => 209170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/209170
Process for forming a static-random-access memory cell Feb 27, 1994 Issued
Array ( [id] => 3428258 [patent_doc_number] => 05455189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Method of forming BICMOS structures' [patent_app_type] => 1 [patent_app_number] => 8/203236 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5776 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455189.pdf [firstpage_image] =>[orig_patent_app_number] => 203236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/203236
Method of forming BICMOS structures Feb 27, 1994 Issued
Array ( [id] => 3424648 [patent_doc_number] => 05422290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Method of fabricating BiCMOS structures' [patent_app_type] => 1 [patent_app_number] => 8/202328 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5860 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422290.pdf [firstpage_image] =>[orig_patent_app_number] => 202328 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/202328
Method of fabricating BiCMOS structures Feb 27, 1994 Issued
Array ( [id] => 3122775 [patent_doc_number] => 05436180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Method for reducing base resistance in epitaxial-based bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/203094 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2455 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436180.pdf [firstpage_image] =>[orig_patent_app_number] => 203094 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/203094
Method for reducing base resistance in epitaxial-based bipolar transistor Feb 27, 1994 Issued
Array ( [id] => 3070898 [patent_doc_number] => 05360746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/193742 [patent_app_country] => US [patent_app_date] => 1994-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 38 [patent_no_of_words] => 8039 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/360/05360746.pdf [firstpage_image] =>[orig_patent_app_number] => 193742 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/193742
Method of fabricating a semiconductor device Feb 8, 1994 Issued
Array ( [id] => 2993417 [patent_doc_number] => 05366918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Method for fabricating a split polysilicon SRAM cell' [patent_app_type] => 1 [patent_app_number] => 8/192366 [patent_app_country] => US [patent_app_date] => 1994-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2998 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/366/05366918.pdf [firstpage_image] =>[orig_patent_app_number] => 192366 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/192366
Method for fabricating a split polysilicon SRAM cell Feb 6, 1994 Issued
Array ( [id] => 3441138 [patent_doc_number] => 05429989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Process for fabricating a metallization structure in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/190966 [patent_app_country] => US [patent_app_date] => 1994-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3052 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/429/05429989.pdf [firstpage_image] =>[orig_patent_app_number] => 190966 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/190966
Process for fabricating a metallization structure in a semiconductor device Feb 2, 1994 Issued
Array ( [id] => 3478169 [patent_doc_number] => 05399510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/190496 [patent_app_country] => US [patent_app_date] => 1994-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 3593 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399510.pdf [firstpage_image] =>[orig_patent_app_number] => 190496 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/190496
Method of fabricating a semiconductor device Feb 1, 1994 Issued
Array ( [id] => 3117366 [patent_doc_number] => 05380670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/190494 [patent_app_country] => US [patent_app_date] => 1994-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3801 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/380/05380670.pdf [firstpage_image] =>[orig_patent_app_number] => 190494 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/190494
Method of fabricating a semiconductor device Feb 1, 1994 Issued
Array ( [id] => 3417588 [patent_doc_number] => 05434107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Method for planarization' [patent_app_type] => 1 [patent_app_number] => 8/188498 [patent_app_country] => US [patent_app_date] => 1994-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3880 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434107.pdf [firstpage_image] =>[orig_patent_app_number] => 188498 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/188498
Method for planarization Jan 27, 1994 Issued
Array ( [id] => 3424846 [patent_doc_number] => 05422303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Method for manufacturing a laterally limited, single-crystal region on a substrate and the employment thereof for the manufacture of an MOS transistor and a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/185514 [patent_app_country] => US [patent_app_date] => 1994-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5508 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422303.pdf [firstpage_image] =>[orig_patent_app_number] => 185514 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/185514
Method for manufacturing a laterally limited, single-crystal region on a substrate and the employment thereof for the manufacture of an MOS transistor and a bipolar transistor Jan 23, 1994 Issued
Array ( [id] => 3054110 [patent_doc_number] => 05356822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-18 [patent_title] => 'Method for making all complementary BiCDMOS devices' [patent_app_type] => 1 [patent_app_number] => 8/184516 [patent_app_country] => US [patent_app_date] => 1994-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2418 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/356/05356822.pdf [firstpage_image] =>[orig_patent_app_number] => 184516 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/184516
Method for making all complementary BiCDMOS devices Jan 20, 1994 Issued
Array ( [id] => 3070971 [patent_doc_number] => 05360750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Method of fabricating lateral bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/180622 [patent_app_country] => US [patent_app_date] => 1994-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 1431 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/360/05360750.pdf [firstpage_image] =>[orig_patent_app_number] => 180622 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/180622
Method of fabricating lateral bipolar transistors Jan 12, 1994 Issued
Array ( [id] => 3453013 [patent_doc_number] => 05451530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Method for forming integrated circuits having buried doped regions' [patent_app_type] => 1 [patent_app_number] => 8/179849 [patent_app_country] => US [patent_app_date] => 1994-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 4700 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451530.pdf [firstpage_image] =>[orig_patent_app_number] => 179849 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/179849
Method for forming integrated circuits having buried doped regions Jan 10, 1994 Issued
Array ( [id] => 2993690 [patent_doc_number] => 05362657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Lateral complementary heterojunction bipolar transistor and processing procedure' [patent_app_type] => 1 [patent_app_number] => 8/180753 [patent_app_country] => US [patent_app_date] => 1994-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2602 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/362/05362657.pdf [firstpage_image] =>[orig_patent_app_number] => 180753 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/180753
Lateral complementary heterojunction bipolar transistor and processing procedure Jan 9, 1994 Issued
Array ( [id] => 3447841 [patent_doc_number] => 05424227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-13 [patent_title] => 'Method of manufacture of silicon-germanium heterobipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/178138 [patent_app_country] => US [patent_app_date] => 1994-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2046 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/424/05424227.pdf [firstpage_image] =>[orig_patent_app_number] => 178138 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/178138
Method of manufacture of silicon-germanium heterobipolar transistors Jan 5, 1994 Issued
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