Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3122758 [patent_doc_number] => 05436179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Semiconductor process for manufacturing semiconductor devices with increased operating voltages' [patent_app_type] => 1 [patent_app_number] => 8/177888 [patent_app_country] => US [patent_app_date] => 1994-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 5104 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436179.pdf [firstpage_image] =>[orig_patent_app_number] => 177888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/177888
Semiconductor process for manufacturing semiconductor devices with increased operating voltages Jan 4, 1994 Issued
Array ( [id] => 3417346 [patent_doc_number] => 05434092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Method for fabricating a triple self-aligned bipolar junction transistor' [patent_app_type] => 1 [patent_app_number] => 8/177174 [patent_app_country] => US [patent_app_date] => 1994-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3860 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434092.pdf [firstpage_image] =>[orig_patent_app_number] => 177174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/177174
Method for fabricating a triple self-aligned bipolar junction transistor Jan 3, 1994 Issued
Array ( [id] => 3112977 [patent_doc_number] => 05409846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Method of fabricating a semiconductor device including heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/175664 [patent_app_country] => US [patent_app_date] => 1993-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 5653 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/409/05409846.pdf [firstpage_image] =>[orig_patent_app_number] => 175664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/175664
Method of fabricating a semiconductor device including heterojunction bipolar transistor Dec 29, 1993 Issued
Array ( [id] => 2999625 [patent_doc_number] => 05374329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Process for producing a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 8/173947 [patent_app_country] => US [patent_app_date] => 1993-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 20673 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/374/05374329.pdf [firstpage_image] =>[orig_patent_app_number] => 173947 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/173947
Process for producing a semiconductor wafer Dec 27, 1993 Issued
Array ( [id] => 3588990 [patent_doc_number] => 05496743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Method of making an article comprising a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/171504 [patent_app_country] => US [patent_app_date] => 1993-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5882 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/496/05496743.pdf [firstpage_image] =>[orig_patent_app_number] => 171504 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/171504
Method of making an article comprising a semiconductor device Dec 20, 1993 Issued
Array ( [id] => 3443975 [patent_doc_number] => 05420050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Method of enhancing the current gain of bipolar junction transistors' [patent_app_type] => 1 [patent_app_number] => 8/170542 [patent_app_country] => US [patent_app_date] => 1993-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 4904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420050.pdf [firstpage_image] =>[orig_patent_app_number] => 170542 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/170542
Method of enhancing the current gain of bipolar junction transistors Dec 19, 1993 Issued
Array ( [id] => 3426779 [patent_doc_number] => 05403758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Process of forming a bipolar type semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/164794 [patent_app_country] => US [patent_app_date] => 1993-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 48 [patent_no_of_words] => 13320 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/403/05403758.pdf [firstpage_image] =>[orig_patent_app_number] => 164794 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/164794
Process of forming a bipolar type semiconductor device Dec 9, 1993 Issued
Array ( [id] => 3458895 [patent_doc_number] => 05441903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'BiCMOS process for supporting merged devices' [patent_app_type] => 1 [patent_app_number] => 8/161960 [patent_app_country] => US [patent_app_date] => 1993-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 1971 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/441/05441903.pdf [firstpage_image] =>[orig_patent_app_number] => 161960 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/161960
BiCMOS process for supporting merged devices Dec 2, 1993 Issued
Array ( [id] => 3421864 [patent_doc_number] => 05389561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Method for making SOI type bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/161498 [patent_app_country] => US [patent_app_date] => 1993-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 58 [patent_no_of_words] => 10104 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/389/05389561.pdf [firstpage_image] =>[orig_patent_app_number] => 161498 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/161498
Method for making SOI type bipolar transistor Dec 1, 1993 Issued
Array ( [id] => 3421767 [patent_doc_number] => 05389554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Method for fabricating microwave heterojunction bipolar transistors with emitters designed for high power applications' [patent_app_type] => 1 [patent_app_number] => 8/159758 [patent_app_country] => US [patent_app_date] => 1993-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 4154 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/389/05389554.pdf [firstpage_image] =>[orig_patent_app_number] => 159758 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/159758
Method for fabricating microwave heterojunction bipolar transistors with emitters designed for high power applications Nov 29, 1993 Issued
Array ( [id] => 3480424 [patent_doc_number] => 05405790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Method of forming a semiconductor structure having MOS, bipolar, and varactor devices' [patent_app_type] => 1 [patent_app_number] => 8/155882 [patent_app_country] => US [patent_app_date] => 1993-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 6972 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/405/05405790.pdf [firstpage_image] =>[orig_patent_app_number] => 155882 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/155882
Method of forming a semiconductor structure having MOS, bipolar, and varactor devices Nov 22, 1993 Issued
Array ( [id] => 2993224 [patent_doc_number] => 05366908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Process for fabricating a MOS device having protection against electrostatic discharge' [patent_app_type] => 1 [patent_app_number] => 8/152640 [patent_app_country] => US [patent_app_date] => 1993-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2420 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/366/05366908.pdf [firstpage_image] =>[orig_patent_app_number] => 152640 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/152640
Process for fabricating a MOS device having protection against electrostatic discharge Nov 15, 1993 Issued
Array ( [id] => 3425304 [patent_doc_number] => 05416040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'Method of making an integrated field effect transistor and resonant tunneling diode' [patent_app_type] => 1 [patent_app_number] => 8/153116 [patent_app_country] => US [patent_app_date] => 1993-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 2533 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416040.pdf [firstpage_image] =>[orig_patent_app_number] => 153116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/153116
Method of making an integrated field effect transistor and resonant tunneling diode Nov 14, 1993 Issued
Array ( [id] => 3036720 [patent_doc_number] => 05372954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-13 [patent_title] => 'Method of fabricating an insulated gate bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/148628 [patent_app_country] => US [patent_app_date] => 1993-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 6312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/372/05372954.pdf [firstpage_image] =>[orig_patent_app_number] => 148628 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/148628
Method of fabricating an insulated gate bipolar transistor Nov 7, 1993 Issued
Array ( [id] => 3459896 [patent_doc_number] => 05391504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Method for producing integrated quasi-complementary bipolar transistors and field effect transistors' [patent_app_type] => 1 [patent_app_number] => 8/147108 [patent_app_country] => US [patent_app_date] => 1993-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2199 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/391/05391504.pdf [firstpage_image] =>[orig_patent_app_number] => 147108 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/147108
Method for producing integrated quasi-complementary bipolar transistors and field effect transistors Nov 2, 1993 Issued
Array ( [id] => 2989045 [patent_doc_number] => 05346838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Method for fabricating an insulated gate control thyristor' [patent_app_type] => 1 [patent_app_number] => 8/141924 [patent_app_country] => US [patent_app_date] => 1993-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5820 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/346/05346838.pdf [firstpage_image] =>[orig_patent_app_number] => 141924 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/141924
Method for fabricating an insulated gate control thyristor Oct 27, 1993 Issued
Array ( [id] => 3566687 [patent_doc_number] => 05484745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Method for forming a semiconductor sensor' [patent_app_type] => 1 [patent_app_number] => 8/141055 [patent_app_country] => US [patent_app_date] => 1993-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 1405 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/484/05484745.pdf [firstpage_image] =>[orig_patent_app_number] => 141055 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/141055
Method for forming a semiconductor sensor Oct 25, 1993 Issued
Array ( [id] => 3480411 [patent_doc_number] => 05405789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Method of manufacturing a semiconductor device whereby a laterally bounded semiconductor zone is formed in a semiconductor body in a self-aligning manner' [patent_app_type] => 1 [patent_app_number] => 8/141888 [patent_app_country] => US [patent_app_date] => 1993-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 39 [patent_no_of_words] => 7142 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/405/05405789.pdf [firstpage_image] =>[orig_patent_app_number] => 141888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/141888
Method of manufacturing a semiconductor device whereby a laterally bounded semiconductor zone is formed in a semiconductor body in a self-aligning manner Oct 21, 1993 Issued
Array ( [id] => 3026802 [patent_doc_number] => 05348896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Method for fabricating a BiCMOS device' [patent_app_type] => 1 [patent_app_number] => 8/128380 [patent_app_country] => US [patent_app_date] => 1993-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2772 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 483 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/348/05348896.pdf [firstpage_image] =>[orig_patent_app_number] => 128380 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/128380
Method for fabricating a BiCMOS device Sep 27, 1993 Issued
Array ( [id] => 3004331 [patent_doc_number] => 05374568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Method for forming a base link in a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/125986 [patent_app_country] => US [patent_app_date] => 1993-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2816 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/374/05374568.pdf [firstpage_image] =>[orig_patent_app_number] => 125986 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/125986
Method for forming a base link in a bipolar transistor Sep 22, 1993 Issued
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