| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3444230
[patent_doc_number] => 05420067
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-30
[patent_title] => 'Method of fabricatring sub-half-micron trenches and holes'
[patent_app_type] => 1
[patent_app_number] => 8/123665
[patent_app_country] => US
[patent_app_date] => 1993-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 43
[patent_no_of_words] => 9125
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/420/05420067.pdf
[firstpage_image] =>[orig_patent_app_number] => 123665
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/123665 | Method of fabricatring sub-half-micron trenches and holes | Sep 19, 1993 | Issued |
Array
(
[id] => 3057385
[patent_doc_number] => 05350712
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-27
[patent_title] => 'Method of manufacturing a semiconductor IC device having multilayer interconnection structure'
[patent_app_type] => 1
[patent_app_number] => 8/121554
[patent_app_country] => US
[patent_app_date] => 1993-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 4042
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/350/05350712.pdf
[firstpage_image] =>[orig_patent_app_number] => 121554
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/121554 | Method of manufacturing a semiconductor IC device having multilayer interconnection structure | Sep 15, 1993 | Issued |
Array
(
[id] => 3416641
[patent_doc_number] => 05453389
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-26
[patent_title] => 'Defect-free bipolar process'
[patent_app_type] => 1
[patent_app_number] => 8/113772
[patent_app_country] => US
[patent_app_date] => 1993-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 20
[patent_no_of_words] => 2423
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/453/05453389.pdf
[firstpage_image] =>[orig_patent_app_number] => 113772
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/113772 | Defect-free bipolar process | Aug 26, 1993 | Issued |
Array
(
[id] => 2996453
[patent_doc_number] => 05358883
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-25
[patent_title] => 'Lateral bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 8/105490
[patent_app_country] => US
[patent_app_date] => 1993-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2870
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/358/05358883.pdf
[firstpage_image] =>[orig_patent_app_number] => 105490
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/105490 | Lateral bipolar transistor | Aug 11, 1993 | Issued |
Array
(
[id] => 3054093
[patent_doc_number] => 05356821
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-18
[patent_title] => 'Method for manufacturing semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/104907
[patent_app_country] => US
[patent_app_date] => 1993-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 22
[patent_no_of_words] => 6740
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/356/05356821.pdf
[firstpage_image] =>[orig_patent_app_number] => 104907
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/104907 | Method for manufacturing semiconductor integrated circuit device | Aug 11, 1993 | Issued |
Array
(
[id] => 3054179
[patent_doc_number] => 05356826
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-18
[patent_title] => 'Method of manufacturing semiconductor device provided with capacitor and resistor'
[patent_app_type] => 1
[patent_app_number] => 8/102586
[patent_app_country] => US
[patent_app_date] => 1993-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 3606
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/356/05356826.pdf
[firstpage_image] =>[orig_patent_app_number] => 102586
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/102586 | Method of manufacturing semiconductor device provided with capacitor and resistor | Aug 4, 1993 | Issued |
Array
(
[id] => 3027593
[patent_doc_number] => 05316966
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Method of providing mask alignment marks'
[patent_app_type] => 1
[patent_app_number] => 8/101797
[patent_app_country] => US
[patent_app_date] => 1993-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 2940
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/316/05316966.pdf
[firstpage_image] =>[orig_patent_app_number] => 101797
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/101797 | Method of providing mask alignment marks | Aug 2, 1993 | Issued |
| 08/095943 | METHOD OF MAKING AN INTEGRATED CIRCUIT WITH COMPLEMENTARY BIPOLAR TRANSISTORS | Jul 21, 1993 | Pending |
| 08/092888 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME AND METHOD FOR FORMING TRANSPARENT CONDUCTIVE FILM | Jul 18, 1993 | Pending |
Array
(
[id] => 3006667
[patent_doc_number] => 05354708
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-11
[patent_title] => 'Method of nitrogen doping of II-VI semiconductor compounds during epitaxial growth using an amine'
[patent_app_type] => 1
[patent_app_number] => 8/091634
[patent_app_country] => US
[patent_app_date] => 1993-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2147
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/354/05354708.pdf
[firstpage_image] =>[orig_patent_app_number] => 091634
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/091634 | Method of nitrogen doping of II-VI semiconductor compounds during epitaxial growth using an amine | Jul 13, 1993 | Issued |
| 08/090516 | PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING ARSENIC EMITTERS | Jul 11, 1993 | Pending |
Array
(
[id] => 3440685
[patent_doc_number] => 05429959
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Process for simultaneously fabricating a bipolar transistor and a field-effect transistor'
[patent_app_type] => 1
[patent_app_number] => 8/089394
[patent_app_country] => US
[patent_app_date] => 1993-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 99
[patent_no_of_words] => 26192
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/429/05429959.pdf
[firstpage_image] =>[orig_patent_app_number] => 089394
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/089394 | Process for simultaneously fabricating a bipolar transistor and a field-effect transistor | Jul 8, 1993 | Issued |
Array
(
[id] => 3091493
[patent_doc_number] => 05290716
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-01
[patent_title] => 'Method of manufacturing semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/087352
[patent_app_country] => US
[patent_app_date] => 1993-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 29
[patent_no_of_words] => 8469
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/290/05290716.pdf
[firstpage_image] =>[orig_patent_app_number] => 087352
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/087352 | Method of manufacturing semiconductor devices | Jul 7, 1993 | Issued |
Array
(
[id] => 3495804
[patent_doc_number] => 05532177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-02
[patent_title] => 'Method for forming electron emitters'
[patent_app_type] => 1
[patent_app_number] => 8/089166
[patent_app_country] => US
[patent_app_date] => 1993-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2143
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/532/05532177.pdf
[firstpage_image] =>[orig_patent_app_number] => 089166
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/089166 | Method for forming electron emitters | Jul 6, 1993 | Issued |
Array
(
[id] => 3027435
[patent_doc_number] => 05316957
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Method of forming a recessed contact bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 8/085676
[patent_app_country] => US
[patent_app_date] => 1993-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3392
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/316/05316957.pdf
[firstpage_image] =>[orig_patent_app_number] => 085676
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/085676 | Method of forming a recessed contact bipolar transistor | Jun 29, 1993 | Issued |
| 08/085972 | INTERCONNECT FOR INTEGRATED CIRCUITS | Jun 29, 1993 | Pending |
Array
(
[id] => 3421753
[patent_doc_number] => 05389553
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-14
[patent_title] => 'Methods for fabrication of transistors'
[patent_app_type] => 1
[patent_app_number] => 8/085436
[patent_app_country] => US
[patent_app_date] => 1993-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 4210
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/389/05389553.pdf
[firstpage_image] =>[orig_patent_app_number] => 085436
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/085436 | Methods for fabrication of transistors | Jun 29, 1993 | Issued |
Array
(
[id] => 3033732
[patent_doc_number] => 05300443
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-05
[patent_title] => 'Method for fabricating complementary enhancement and depletion mode field effect transistors on a single substrate'
[patent_app_type] => 1
[patent_app_number] => 8/094541
[patent_app_country] => US
[patent_app_date] => 1993-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 2790
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/300/05300443.pdf
[firstpage_image] =>[orig_patent_app_number] => 094541
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/094541 | Method for fabricating complementary enhancement and depletion mode field effect transistors on a single substrate | Jun 29, 1993 | Issued |
Array
(
[id] => 3071424
[patent_doc_number] => 05364803
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-15
[patent_title] => 'Method of preventing fluorine-induced gate oxide degradation in WSi.sub.x polycide structure'
[patent_app_type] => 1
[patent_app_number] => 8/080304
[patent_app_country] => US
[patent_app_date] => 1993-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1557
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/364/05364803.pdf
[firstpage_image] =>[orig_patent_app_number] => 080304
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/080304 | Method of preventing fluorine-induced gate oxide degradation in WSi.sub.x polycide structure | Jun 23, 1993 | Issued |
Array
(
[id] => 3440672
[patent_doc_number] => 05429958
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Process for forming twin well CMOS integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/080744
[patent_app_country] => US
[patent_app_date] => 1993-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 5004
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/429/05429958.pdf
[firstpage_image] =>[orig_patent_app_number] => 080744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/080744 | Process for forming twin well CMOS integrated circuits | Jun 21, 1993 | Issued |