
Hua Jasmine Song
Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )
| Most Active Art Unit | 2133 |
| Art Unit(s) | 2131, 2189, 2187, 2138, 2133, 2188 |
| Total Applications | 1393 |
| Issued Applications | 1256 |
| Pending Applications | 72 |
| Abandoned Applications | 80 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3006452
[patent_doc_number] => 05330920
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-19
[patent_title] => 'Method of controlling gate oxide thickness in the fabrication of semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/077570
[patent_app_country] => US
[patent_app_date] => 1993-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1292
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[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/330/05330920.pdf
[firstpage_image] =>[orig_patent_app_number] => 077570
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/077570 | Method of controlling gate oxide thickness in the fabrication of semiconductor devices | Jun 14, 1993 | Issued |
| 08/073645 | SEMICONDUCTOR DEVICE HAVING A BOROSILICATE GLASS SPACER AND METHOD OF FABRICATION | Jun 7, 1993 | Pending |
Array
(
[id] => 2993567
[patent_doc_number] => 05366926
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-22
[patent_title] => 'Low temperature process for laser dehydrogenation and crystallization of amorphous silicon'
[patent_app_type] => 1
[patent_app_number] => 8/073022
[patent_app_country] => US
[patent_app_date] => 1993-06-07
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 073022
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/073022 | Low temperature process for laser dehydrogenation and crystallization of amorphous silicon | Jun 6, 1993 | Issued |
Array
(
[id] => 3052101
[patent_doc_number] => 05344785
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-06
[patent_title] => 'Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate'
[patent_app_type] => 1
[patent_app_number] => 8/072653
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[patent_app_date] => 1993-06-03
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[firstpage_image] =>[orig_patent_app_number] => 072653
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/072653 | Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate | Jun 2, 1993 | Issued |
Array
(
[id] => 3410950
[patent_doc_number] => 05411903
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-02
[patent_title] => 'Self-aligned complementary HFETS'
[patent_app_type] => 1
[patent_app_number] => 8/069648
[patent_app_country] => US
[patent_app_date] => 1993-06-01
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 069648
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/069648 | Self-aligned complementary HFETS | May 31, 1993 | Issued |
Array
(
[id] => 2993620
[patent_doc_number] => 05366929
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-22
[patent_title] => 'Method for making reliable selective via fills'
[patent_app_type] => 1
[patent_app_number] => 8/068900
[patent_app_country] => US
[patent_app_date] => 1993-05-28
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[pdf_file] => patents/05/366/05366929.pdf
[firstpage_image] =>[orig_patent_app_number] => 068900
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/068900 | Method for making reliable selective via fills | May 27, 1993 | Issued |
Array
(
[id] => 3070364
[patent_doc_number] => 05336631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-09
[patent_title] => 'Method of making and trimming ballast resistors and barrier metal in microwave power transistors'
[patent_app_type] => 1
[patent_app_number] => 8/067192
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[patent_app_date] => 1993-05-26
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[firstpage_image] =>[orig_patent_app_number] => 067192
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/067192 | Method of making and trimming ballast resistors and barrier metal in microwave power transistors | May 25, 1993 | Issued |
Array
(
[id] => 3073531
[patent_doc_number] => 05296391
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'Method of manufacturing a bipolar transistor having thin base region'
[patent_app_type] => 1
[patent_app_number] => 8/067017
[patent_app_country] => US
[patent_app_date] => 1993-05-26
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[pdf_file] => patents/05/296/05296391.pdf
[firstpage_image] =>[orig_patent_app_number] => 067017
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/067017 | Method of manufacturing a bipolar transistor having thin base region | May 25, 1993 | Issued |
Array
(
[id] => 3004264
[patent_doc_number] => 05374567
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-20
[patent_title] => 'Operational amplifier using bipolar junction transistors in silicon-on-sapphire'
[patent_app_type] => 1
[patent_app_number] => 8/065321
[patent_app_country] => US
[patent_app_date] => 1993-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 3541
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[pdf_file] => patents/05/374/05374567.pdf
[firstpage_image] =>[orig_patent_app_number] => 065321
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/065321 | Operational amplifier using bipolar junction transistors in silicon-on-sapphire | May 19, 1993 | Issued |
Array
(
[id] => 3052917
[patent_doc_number] => 05350486
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-27
[patent_title] => 'Semiconductor planarization process'
[patent_app_type] => 1
[patent_app_number] => 8/065122
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[patent_app_date] => 1993-05-20
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[pdf_file] => patents/05/350/05350486.pdf
[firstpage_image] =>[orig_patent_app_number] => 065122
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/065122 | Semiconductor planarization process | May 19, 1993 | Issued |
Array
(
[id] => 3073512
[patent_doc_number] => 05296390
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'Method for fabricating a semiconductor device having a vertical channel of carriers'
[patent_app_type] => 1
[patent_app_number] => 8/061250
[patent_app_country] => US
[patent_app_date] => 1993-05-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/296/05296390.pdf
[firstpage_image] =>[orig_patent_app_number] => 061250
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/061250 | Method for fabricating a semiconductor device having a vertical channel of carriers | May 16, 1993 | Issued |
Array
(
[id] => 3012488
[patent_doc_number] => 05332696
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-26
[patent_title] => 'Method for manufacturing a silicon layer having increased surface area'
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[patent_app_date] => 1993-05-14
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[pdf_file] => patents/05/332/05332696.pdf
[firstpage_image] =>[orig_patent_app_number] => 062966
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/062966 | Method for manufacturing a silicon layer having increased surface area | May 13, 1993 | Issued |
Array
(
[id] => 3057156
[patent_doc_number] => 05350699
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[patent_kind] => NA
[patent_issue_date] => 1994-09-27
[patent_title] => 'Method of manufacturing a hetero-junction bi-polar transistor'
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[patent_app_number] => 8/059268
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Array
(
[id] => 2993707
[patent_doc_number] => 05362658
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[patent_title] => 'Method for producing semiconductor device'
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Array
(
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[patent_title] => 'Method of forming an insulated gate semiconductor device'
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Array
(
[id] => 3093223
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[patent_title] => 'Process for producing a semiconductor memory device having memory cells including transistors and capacitors'
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Array
(
[id] => 3032547
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Array
(
[id] => 3014679
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Array
(
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[patent_issue_date] => 1994-10-18
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Array
(
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