Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3083285 [patent_doc_number] => 05279977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Method of manufacturing a semiconductor device for extracting a signal used to monitor potential of a high voltage island' [patent_app_type] => 1 [patent_app_number] => 7/997924 [patent_app_country] => US [patent_app_date] => 1992-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 42 [patent_no_of_words] => 8868 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/279/05279977.pdf [firstpage_image] =>[orig_patent_app_number] => 997924 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/997924
Method of manufacturing a semiconductor device for extracting a signal used to monitor potential of a high voltage island Dec 28, 1992 Issued
Array ( [id] => 3083300 [patent_doc_number] => 05279978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Process for making BiCMOS device having an SOI substrate' [patent_app_type] => 1 [patent_app_number] => 7/993282 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4180 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/279/05279978.pdf [firstpage_image] =>[orig_patent_app_number] => 993282 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993282
Process for making BiCMOS device having an SOI substrate Dec 17, 1992 Issued
Array ( [id] => 3027559 [patent_doc_number] => 05316964 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Method of forming integrated circuits with diffused resistors in isolation regions' [patent_app_type] => 1 [patent_app_number] => 7/988342 [patent_app_country] => US [patent_app_date] => 1992-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 916 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/316/05316964.pdf [firstpage_image] =>[orig_patent_app_number] => 988342 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/988342
Method of forming integrated circuits with diffused resistors in isolation regions Dec 7, 1992 Issued
Array ( [id] => 3067077 [patent_doc_number] => 05296047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Epitaxial silicon starting material' [patent_app_type] => 1 [patent_app_number] => 7/984725 [patent_app_country] => US [patent_app_date] => 1992-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1111 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296047.pdf [firstpage_image] =>[orig_patent_app_number] => 984725 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/984725
Epitaxial silicon starting material Nov 30, 1992 Issued
07/983000 SELECTIVE TRENCHING AND EMITTER BASE SELF ALIGNMENT STRUCTURE Nov 29, 1992 Abandoned
07/982452 METHOD FOR PRODUCING A BIPOLAR JUNCTION TRANSISTOR Nov 26, 1992 Abandoned
07/982096 LATERAL COMPLEMENTARY HETEROJUNCTION BIPOLAR TRANSISTOR AND PROCESSING PROCEDURE Nov 24, 1992 Abandoned
Array ( [id] => 3056825 [patent_doc_number] => 05338695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Making walled emitter bipolar transistor with reduced base narrowing' [patent_app_type] => 1 [patent_app_number] => 7/981188 [patent_app_country] => US [patent_app_date] => 1992-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2665 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/338/05338695.pdf [firstpage_image] =>[orig_patent_app_number] => 981188 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/981188
Making walled emitter bipolar transistor with reduced base narrowing Nov 23, 1992 Issued
Array ( [id] => 2960380 [patent_doc_number] => 05273913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'High performance lateral PNP transistor with buried base contact' [patent_app_type] => 1 [patent_app_number] => 7/980155 [patent_app_country] => US [patent_app_date] => 1992-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2043 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/273/05273913.pdf [firstpage_image] =>[orig_patent_app_number] => 980155 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/980155
High performance lateral PNP transistor with buried base contact Nov 22, 1992 Issued
Array ( [id] => 2976212 [patent_doc_number] => 05252503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Techniques for forming isolation structures' [patent_app_type] => 1 [patent_app_number] => 7/979305 [patent_app_country] => US [patent_app_date] => 1992-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4961 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/252/05252503.pdf [firstpage_image] =>[orig_patent_app_number] => 979305 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/979305
Techniques for forming isolation structures Nov 19, 1992 Issued
Array ( [id] => 3086249 [patent_doc_number] => 05278099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Method for manufacturing a semiconductor device having wiring electrodes' [patent_app_type] => 1 [patent_app_number] => 7/976664 [patent_app_country] => US [patent_app_date] => 1992-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2485 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278099.pdf [firstpage_image] =>[orig_patent_app_number] => 976664 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/976664
Method for manufacturing a semiconductor device having wiring electrodes Nov 15, 1992 Issued
Array ( [id] => 3106922 [patent_doc_number] => 05407841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'CBiCMOS fabrication method using sacrificial gate poly' [patent_app_type] => 1 [patent_app_number] => 7/968910 [patent_app_country] => US [patent_app_date] => 1992-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4532 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/407/05407841.pdf [firstpage_image] =>[orig_patent_app_number] => 968910 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/968910
CBiCMOS fabrication method using sacrificial gate poly Oct 29, 1992 Issued
Array ( [id] => 2952208 [patent_doc_number] => 05242843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-07 [patent_title] => 'Method for making a heterojunction bipolar transistor with improved high frequency response' [patent_app_type] => 1 [patent_app_number] => 7/967324 [patent_app_country] => US [patent_app_date] => 1992-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1996 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/242/05242843.pdf [firstpage_image] =>[orig_patent_app_number] => 967324 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/967324
Method for making a heterojunction bipolar transistor with improved high frequency response Oct 27, 1992 Issued
Array ( [id] => 3006492 [patent_doc_number] => 05354699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Method of manufacturing semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/964824 [patent_app_country] => US [patent_app_date] => 1992-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 11789 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/354/05354699.pdf [firstpage_image] =>[orig_patent_app_number] => 964824 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/964824
Method of manufacturing semiconductor integrated circuit device Oct 21, 1992 Issued
Array ( [id] => 2960416 [patent_doc_number] => 05273915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Method for fabricating bipolar junction and MOS transistors on SOI' [patent_app_type] => 1 [patent_app_number] => 7/956224 [patent_app_country] => US [patent_app_date] => 1992-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/273/05273915.pdf [firstpage_image] =>[orig_patent_app_number] => 956224 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/956224
Method for fabricating bipolar junction and MOS transistors on SOI Oct 4, 1992 Issued
Array ( [id] => 3043317 [patent_doc_number] => 05286664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Method for fabricating the LDD-MOSFET' [patent_app_type] => 1 [patent_app_number] => 7/955356 [patent_app_country] => US [patent_app_date] => 1992-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 3481 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/286/05286664.pdf [firstpage_image] =>[orig_patent_app_number] => 955356 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/955356
Method for fabricating the LDD-MOSFET Sep 30, 1992 Issued
Array ( [id] => 2890248 [patent_doc_number] => 05270230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Method for making a conductivity modulation MOSFET' [patent_app_type] => 1 [patent_app_number] => 7/952989 [patent_app_country] => US [patent_app_date] => 1992-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5261 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270230.pdf [firstpage_image] =>[orig_patent_app_number] => 952989 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/952989
Method for making a conductivity modulation MOSFET Sep 28, 1992 Issued
Array ( [id] => 2893430 [patent_doc_number] => 05272098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-21 [patent_title] => 'Vertical and lateral insulated-gate, field-effect transistors, systems and methods' [patent_app_type] => 1 [patent_app_number] => 7/952220 [patent_app_country] => US [patent_app_date] => 1992-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 99 [patent_no_of_words] => 26574 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/272/05272098.pdf [firstpage_image] =>[orig_patent_app_number] => 952220 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/952220
Vertical and lateral insulated-gate, field-effect transistors, systems and methods Sep 27, 1992 Issued
07/952483 BIPOLAR TRANSISTORS, SYSTEMS AND METHODS Sep 27, 1992 Abandoned
Array ( [id] => 3032495 [patent_doc_number] => 05328857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Method of forming a bilevel, self aligned, low base resistance semiconductor structure' [patent_app_type] => 1 [patent_app_number] => 7/951162 [patent_app_country] => US [patent_app_date] => 1992-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2102 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/328/05328857.pdf [firstpage_image] =>[orig_patent_app_number] => 951162 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/951162
Method of forming a bilevel, self aligned, low base resistance semiconductor structure Sep 24, 1992 Issued
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