| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Method of manufacturing a semiconductor device for extracting a signal used to monitor potential of a high voltage island'
[patent_app_type] => 1
[patent_app_number] => 7/997924
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Array
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[patent_doc_number] => 05279978
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Process for making BiCMOS device having an SOI substrate'
[patent_app_type] => 1
[patent_app_number] => 7/993282
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[patent_app_date] => 1992-12-18
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[firstpage_image] =>[orig_patent_app_number] => 993282
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/993282 | Process for making BiCMOS device having an SOI substrate | Dec 17, 1992 | Issued |
Array
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[id] => 3027559
[patent_doc_number] => 05316964
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Method of forming integrated circuits with diffused resistors in isolation regions'
[patent_app_type] => 1
[patent_app_number] => 7/988342
[patent_app_country] => US
[patent_app_date] => 1992-12-08
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[firstpage_image] =>[orig_patent_app_number] => 988342
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/988342 | Method of forming integrated circuits with diffused resistors in isolation regions | Dec 7, 1992 | Issued |
Array
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[id] => 3067077
[patent_doc_number] => 05296047
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'Epitaxial silicon starting material'
[patent_app_type] => 1
[patent_app_number] => 7/984725
[patent_app_country] => US
[patent_app_date] => 1992-12-01
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 984725
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/984725 | Epitaxial silicon starting material | Nov 30, 1992 | Issued |
| 07/983000 | SELECTIVE TRENCHING AND EMITTER BASE SELF ALIGNMENT STRUCTURE | Nov 29, 1992 | Abandoned |
| 07/982452 | METHOD FOR PRODUCING A BIPOLAR JUNCTION TRANSISTOR | Nov 26, 1992 | Abandoned |
| 07/982096 | LATERAL COMPLEMENTARY HETEROJUNCTION BIPOLAR TRANSISTOR AND PROCESSING PROCEDURE | Nov 24, 1992 | Abandoned |
Array
(
[id] => 3056825
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[patent_kind] => NA
[patent_issue_date] => 1994-08-16
[patent_title] => 'Making walled emitter bipolar transistor with reduced base narrowing'
[patent_app_type] => 1
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[patent_app_country] => US
[patent_app_date] => 1992-11-24
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Array
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[patent_issue_date] => 1993-12-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/980155 | High performance lateral PNP transistor with buried base contact | Nov 22, 1992 | Issued |
Array
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[id] => 2976212
[patent_doc_number] => 05252503
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-12
[patent_title] => 'Techniques for forming isolation structures'
[patent_app_type] => 1
[patent_app_number] => 7/979305
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[patent_app_date] => 1992-11-20
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[pdf_file] => patents/05/252/05252503.pdf
[firstpage_image] =>[orig_patent_app_number] => 979305
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/979305 | Techniques for forming isolation structures | Nov 19, 1992 | Issued |
Array
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[id] => 3086249
[patent_doc_number] => 05278099
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-11
[patent_title] => 'Method for manufacturing a semiconductor device having wiring electrodes'
[patent_app_type] => 1
[patent_app_number] => 7/976664
[patent_app_country] => US
[patent_app_date] => 1992-11-16
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[firstpage_image] =>[orig_patent_app_number] => 976664
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/976664 | Method for manufacturing a semiconductor device having wiring electrodes | Nov 15, 1992 | Issued |
Array
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[id] => 3106922
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[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'CBiCMOS fabrication method using sacrificial gate poly'
[patent_app_type] => 1
[patent_app_number] => 7/968910
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[firstpage_image] =>[orig_patent_app_number] => 968910
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/968910 | CBiCMOS fabrication method using sacrificial gate poly | Oct 29, 1992 | Issued |
Array
(
[id] => 2952208
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[patent_kind] => NA
[patent_issue_date] => 1993-09-07
[patent_title] => 'Method for making a heterojunction bipolar transistor with improved high frequency response'
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[firstpage_image] =>[orig_patent_app_number] => 967324
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/967324 | Method for making a heterojunction bipolar transistor with improved high frequency response | Oct 27, 1992 | Issued |
Array
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[patent_issue_date] => 1994-10-11
[patent_title] => 'Method of manufacturing semiconductor integrated circuit device'
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[firstpage_image] =>[orig_patent_app_number] => 964824
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/964824 | Method of manufacturing semiconductor integrated circuit device | Oct 21, 1992 | Issued |
Array
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[id] => 2960416
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[patent_issue_date] => 1993-12-28
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[firstpage_image] =>[orig_patent_app_number] => 956224
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Array
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[id] => 3043317
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/955356 | Method for fabricating the LDD-MOSFET | Sep 30, 1992 | Issued |
Array
(
[id] => 2890248
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[patent_title] => 'Method for making a conductivity modulation MOSFET'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/952989 | Method for making a conductivity modulation MOSFET | Sep 28, 1992 | Issued |
Array
(
[id] => 2893430
[patent_doc_number] => 05272098
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[patent_kind] => NA
[patent_issue_date] => 1993-12-21
[patent_title] => 'Vertical and lateral insulated-gate, field-effect transistors, systems and methods'
[patent_app_type] => 1
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[patent_app_date] => 1992-09-28
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[firstpage_image] =>[orig_patent_app_number] => 952220
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/952220 | Vertical and lateral insulated-gate, field-effect transistors, systems and methods | Sep 27, 1992 | Issued |
| 07/952483 | BIPOLAR TRANSISTORS, SYSTEMS AND METHODS | Sep 27, 1992 | Abandoned |
Array
(
[id] => 3032495
[patent_doc_number] => 05328857
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[patent_kind] => NA
[patent_issue_date] => 1994-07-12
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[patent_app_date] => 1992-09-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/951162 | Method of forming a bilevel, self aligned, low base resistance semiconductor structure | Sep 24, 1992 | Issued |