Search

Hua Jasmine Song

Examiner (ID: 6964, Phone: (571)272-4213 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2131, 2189, 2187, 2138, 2133, 2188
Total Applications
1393
Issued Applications
1256
Pending Applications
72
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3019479 [patent_doc_number] => 05326718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Method for manufacturing a laterally limited, single-crystal region on a substrate and the employment thereof for the manufacture of an MOS transistor and a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/950068 [patent_app_country] => US [patent_app_date] => 1992-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5500 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/326/05326718.pdf [firstpage_image] =>[orig_patent_app_number] => 950068 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/950068
Method for manufacturing a laterally limited, single-crystal region on a substrate and the employment thereof for the manufacture of an MOS transistor and a bipolar transistor Sep 22, 1992 Issued
Array ( [id] => 3017715 [patent_doc_number] => 05288656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Method of manufacturing a CCD solid state image sensing device' [patent_app_type] => 1 [patent_app_number] => 7/949130 [patent_app_country] => US [patent_app_date] => 1992-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3175 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/288/05288656.pdf [firstpage_image] =>[orig_patent_app_number] => 949130 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/949130
Method of manufacturing a CCD solid state image sensing device Sep 22, 1992 Issued
Array ( [id] => 3446441 [patent_doc_number] => 05387552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Method of fabrication of PNP structure in a common substrate containing NPN or MOS structures' [patent_app_type] => 1 [patent_app_number] => 7/944593 [patent_app_country] => US [patent_app_date] => 1992-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4596 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387552.pdf [firstpage_image] =>[orig_patent_app_number] => 944593 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/944593
Method of fabrication of PNP structure in a common substrate containing NPN or MOS structures Sep 13, 1992 Issued
Array ( [id] => 2996470 [patent_doc_number] => 05358884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Dual purpose collector contact and isolation scheme for advanced bicmos processes' [patent_app_type] => 1 [patent_app_number] => 7/943840 [patent_app_country] => US [patent_app_date] => 1992-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 1624 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/358/05358884.pdf [firstpage_image] =>[orig_patent_app_number] => 943840 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/943840
Dual purpose collector contact and isolation scheme for advanced bicmos processes Sep 10, 1992 Issued
Array ( [id] => 3019336 [patent_doc_number] => 05326710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Process for fabricating lateral PNP transistor structure and BICMOS IC' [patent_app_type] => 1 [patent_app_number] => 7/942977 [patent_app_country] => US [patent_app_date] => 1992-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/326/05326710.pdf [firstpage_image] =>[orig_patent_app_number] => 942977 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/942977
Process for fabricating lateral PNP transistor structure and BICMOS IC Sep 9, 1992 Issued
Array ( [id] => 3091458 [patent_doc_number] => 05290714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Method of forming semiconductor device including a CMOS structure having double-doped channel regions' [patent_app_type] => 1 [patent_app_number] => 7/941825 [patent_app_country] => US [patent_app_date] => 1992-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 2 [patent_no_of_words] => 6774 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 429 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/290/05290714.pdf [firstpage_image] =>[orig_patent_app_number] => 941825 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/941825
Method of forming semiconductor device including a CMOS structure having double-doped channel regions Sep 7, 1992 Issued
Array ( [id] => 2883745 [patent_doc_number] => 05268315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Implant-free heterojunction bioplar transistor integrated circuit process' [patent_app_type] => 1 [patent_app_number] => 7/940588 [patent_app_country] => US [patent_app_date] => 1992-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 3803 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268315.pdf [firstpage_image] =>[orig_patent_app_number] => 940588 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/940588
Implant-free heterojunction bioplar transistor integrated circuit process Sep 3, 1992 Issued
Array ( [id] => 2960505 [patent_doc_number] => 05273920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Method of fabricating a thin film transistor using hydrogen plasma treatment of the gate dielectric/semiconductor layer interface' [patent_app_type] => 1 [patent_app_number] => 7/939746 [patent_app_country] => US [patent_app_date] => 1992-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2827 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/273/05273920.pdf [firstpage_image] =>[orig_patent_app_number] => 939746 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/939746
Method of fabricating a thin film transistor using hydrogen plasma treatment of the gate dielectric/semiconductor layer interface Sep 1, 1992 Issued
Array ( [id] => 3009375 [patent_doc_number] => 05281546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-25 [patent_title] => 'Method of fabricating a thin film transistor using hydrogen plasma treatment of the intrinsic silicon/doped layer interface' [patent_app_type] => 1 [patent_app_number] => 7/939749 [patent_app_country] => US [patent_app_date] => 1992-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3697 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/281/05281546.pdf [firstpage_image] =>[orig_patent_app_number] => 939749 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/939749
Method of fabricating a thin film transistor using hydrogen plasma treatment of the intrinsic silicon/doped layer interface Sep 1, 1992 Issued
Array ( [id] => 3014699 [patent_doc_number] => 05340754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Method for forming a transistor having a dynamic connection between a substrate and a channel region' [patent_app_type] => 1 [patent_app_number] => 7/940260 [patent_app_country] => US [patent_app_date] => 1992-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 40 [patent_no_of_words] => 9121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/340/05340754.pdf [firstpage_image] =>[orig_patent_app_number] => 940260 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/940260
Method for forming a transistor having a dynamic connection between a substrate and a channel region Sep 1, 1992 Issued
Array ( [id] => 3093589 [patent_doc_number] => 05298438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Method of reducing extrinsic base-collector capacitance in bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/938190 [patent_app_country] => US [patent_app_date] => 1992-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 2173 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298438.pdf [firstpage_image] =>[orig_patent_app_number] => 938190 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/938190
Method of reducing extrinsic base-collector capacitance in bipolar transistors Aug 30, 1992 Issued
Array ( [id] => 3043260 [patent_doc_number] => 05286661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Method of forming a bipolar transistor having an emitter overhang' [patent_app_type] => 1 [patent_app_number] => 7/935508 [patent_app_country] => US [patent_app_date] => 1992-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2401 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/286/05286661.pdf [firstpage_image] =>[orig_patent_app_number] => 935508 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/935508
Method of forming a bipolar transistor having an emitter overhang Aug 25, 1992 Issued
Array ( [id] => 2985178 [patent_doc_number] => 05266508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-30 [patent_title] => 'Process for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/933820 [patent_app_country] => US [patent_app_date] => 1992-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 13 [patent_no_of_words] => 2041 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/266/05266508.pdf [firstpage_image] =>[orig_patent_app_number] => 933820 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/933820
Process for manufacturing semiconductor device Aug 23, 1992 Issued
Array ( [id] => 2963180 [patent_doc_number] => 05258096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Method of forming local etch stop landing pads for simultaneous, self-aligned dry etching of contact vias with various depths' [patent_app_type] => 1 [patent_app_number] => 7/933433 [patent_app_country] => US [patent_app_date] => 1992-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2051 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258096.pdf [firstpage_image] =>[orig_patent_app_number] => 933433 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/933433
Method of forming local etch stop landing pads for simultaneous, self-aligned dry etching of contact vias with various depths Aug 19, 1992 Issued
Array ( [id] => 3017516 [patent_doc_number] => 05302554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Method for producing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/928026 [patent_app_country] => US [patent_app_date] => 1992-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 25 [patent_no_of_words] => 2559 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/302/05302554.pdf [firstpage_image] =>[orig_patent_app_number] => 928026 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/928026
Method for producing semiconductor device Aug 10, 1992 Issued
Array ( [id] => 2890601 [patent_doc_number] => 05270248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Method for forming diffusion junctions in solar cell substrates' [patent_app_type] => 1 [patent_app_number] => 7/926963 [patent_app_country] => US [patent_app_date] => 1992-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 7245 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270248.pdf [firstpage_image] =>[orig_patent_app_number] => 926963 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/926963
Method for forming diffusion junctions in solar cell substrates Aug 6, 1992 Issued
Array ( [id] => 3073573 [patent_doc_number] => 05296393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods' [patent_app_type] => 1 [patent_app_number] => 7/924388 [patent_app_country] => US [patent_app_date] => 1992-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 99 [patent_no_of_words] => 26961 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296393.pdf [firstpage_image] =>[orig_patent_app_number] => 924388 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/924388
Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods Aug 2, 1992 Issued
Array ( [id] => 3095107 [patent_doc_number] => 05318916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Symmetric self-aligned processing' [patent_app_type] => 1 [patent_app_number] => 7/923254 [patent_app_country] => US [patent_app_date] => 1992-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 6657 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/318/05318916.pdf [firstpage_image] =>[orig_patent_app_number] => 923254 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/923254
Symmetric self-aligned processing Jul 30, 1992 Issued
07/923046 INTEGRATED QUASI-COMPLEMENTARY BIPOLAR TRANSISTORS AND FIELD EFFECT TRANSISTORS AND METHOD FOR PRODUCING SAME Jul 30, 1992 Abandoned
Array ( [id] => 3093573 [patent_doc_number] => 05298437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Fabrication process for Schottky barrier diodes on a single poly bipolar process' [patent_app_type] => 1 [patent_app_number] => 7/922341 [patent_app_country] => US [patent_app_date] => 1992-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3828 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298437.pdf [firstpage_image] =>[orig_patent_app_number] => 922341 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/922341
Fabrication process for Schottky barrier diodes on a single poly bipolar process Jul 27, 1992 Issued
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